IDT74FCT3807D/E
3.3V CMOS 1-TO-10 CLOCK DRIVER
TEST CIRCUITS
TEST CONDITIONS
Symbol
VCC = 3.3V ±0.3V
Unit
CL
15
pF
RT
ZOUT of pulse generator
Ω
tR / tF
1 (0V to 3V or 3V to 0V)
ns
DEFINITIONS:
CL = Load capacitance: includes jig and probe capacitance.
RT = Termination resistance: should be equal to ZOUT of the Pulse Generator.
tR / tF = Rise/Fall time of the input stimulus from the Pulse Generator.
TEST WAVEFORMS
INPUT
OUTPUT
tPLH
tR
tPHL
tF
3V
1.5V
0V
VOH
2.0V
1.5V
0.8V VOL
Propagation Delay
INDUSTRIAL TEMPERATURE RANGE
VCC
VIN
Pulse
Generator
D.U.T.
RT
VOUT
15pF
CL
CL = 15pF Circuit
INPUT
OUTPUT 1
OUTPUT 2
tPLH1
tPHL1
tSK(o)
tSK(o)
tPLH2
tPHL2
3V
1.5V
0V
VOH
1.5V
VOL
VOH
1.5V
VOL
tSK(o) = |tPLH2 - tPLH1| or |tPHL2 - tPHL1|
Output Skew - tSK(O)
INPUT
OUTPUT
tPLH
tPHL
tSK(p) = |tPHL - tPLH|
Pulse Skew - tSK(P)
3V
1.5V
0V
VOH
1.5V
VOL
INPUT
PACKAGE 1 OUTPUT
PACKAGE 2 OUTPUT
tPLH1
tPHL1
tSK(PP)
tSK(PP)
tPLH2
tPHL2
3V
1.5V
0V
VOH
1.5V
VOL
VOH
1.5V
VOL
tSK(PP) = |tPLH2 - tPLH1| or |tPHL2 - tPHL1|
Part-to-Part Skew - tSK(PP)
Part-to-Part Skew is for the same package and speed grade.
5