IDT72V3672(2003) Просмотр технического описания (PDF) - Integrated Device Technology
Номер в каталоге
Компоненты Описание
производитель
IDT72V3672 Datasheet PDF : 29 Pages
| |||
IDT72V3652/72V3662/72V3672 3.3V CMOS SyncBiFIFOTM
2,048 x 36 x 2, 4,096 x 36 x 2 and 8,192 x 36 x 2
COMMERCIAL TEMPERATURE RANGE
DESCRIPTION (CONTINUED)
as 6.5ns. Two independent 2,048/4,096/8,192 x 36 dual-port SRAM FIFOs
on board each chip buffer data in opposite directions. Communication between
each port may bypass the FIFOs via two 36-bit mailbox registers. Each mailbox
register has a flag to signal when new mail has been stored.
These devices are a synchronous (clocked) FIFO, meaning each port
employs a synchronous interface. All data transfers through a port are gated
to the LOW-to-HIGH transition of a port clock by enable signals. The clocks for
each port are independent of one another and can be asynchronous or
coincident. The enables for each port are arranged to provide a simple
bidirectional interface between microprocessors and/or buses with synchro-
nous control.
These devices have two modes of operation: In the IDT Standard mode,
the first word written to an empty FIFO is deposited into the memory array. A
read operation is required to access that word (along with all other words
residing in memory). In the First Word Fall Through mode (FWFT), the first
long-word (36-bit wide) written to an empty FIFO appears automatically on the
outputs, no read operation required (Nevertheless, accessing subsequent
words does necessitate a formal read request). The state of the FWFT pin
during FIFO operation determines the mode in use.
Each FIFO has a combined Empty/Output Ready Flag (EFA/ORA and
EFB/ORB) and a combined Full/Input Ready Flag (FFA/IRA and FFB/
IRB). The EF and FF functions are selected in the IDT Standard mode. EF
indicates whether or not the FIFO memory is empty. FF shows whether the
PIN CONFIGURATION
NC 18
B35 19
B34 20
B33 21
B32 22
GND 23
B31 24
B30 25
B29 26
B28 27
B27 28
B26 29
VCC 30
B25 31
B24 32
GND 33
B23 34
B22 35
B21 36
B20 37
B19 38
B18 39
GND 40
B17 41
B16 42
VCC 43
B15 44
B14 45
B13 46
B12 47
GND 48
NC 49
NC 50
*Electrical pin 1 in center of beveled edge. Pin 1 identifier in corner.
NOTES:
1. NC – no internal connection
2. Uses Yamaichi socket IC51-1324-828
PQFP(2) (PQ132-1, order code: PQF)
TOP VIEW
2
116 NC
115 NC
114 A35
113 A34
112 A33
111 A32
110 VCC
109 A31
108 A30
107 GND
106 A29
105 A28
104 A27
103 A26
102 A25
101 A24
100 A23
99 FWFT
98 A22
97 VCC
96 A21
95 A20
94 A19
93 A18
92 GND
91 A17
90 A16
89 A15
88 A14
87 A13
86 VCC
85 A12
84 NC
4660 drw02
Share Link: 