IDT72V36100L6BB Просмотр технического описания (PDF) - Integrated Device Technology
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IDT72V36100L6BB Datasheet PDF : 48 Pages
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3.3 VOLT HIGH-DENSITY SUPERSYNC II™
36-BIT FIFO
65,536 x 36
131,072 x 36
IDT72V36100
IDT72V36110
FEATURES:
• Choose among the following memory organizations:
IDT72V36100 65,536 x 36
IDT72V36110 131,072 x 36
• Higher density, 2Meg and 4Meg SuperSync II FIFOs
• Up to 166 MHz Operation of the Clocks
• User selectable Asynchronous read and/or write ports (PBGA Only)
• User selectable input and output port bus-sizing
- x36 in to x36 out
- x36 in to x18 out
- x36 in to x9 out
- x18 in to x36 out
- x9 in to x36 out
• Big-Endian/Little-Endian user selectable byte representation
• 5V input tolerant
• Fixed, low first word latency
• Zero latency retransmit
• Auto power down minimizes standby power consumption
• Master Reset clears entire FIFO
• Partial Reset clears data, but retains programmable settings
FUNCTIONAL BLOCK DIAGRAM
*Available on the PBGA package only.
• Empty, Full and Half-Full flags signal FIFO status
• Programmable Almost-Empty and Almost-Full flags, each flag can
default to one of eight preselected offsets
• Selectable synchronous/asynchronous timing modes for Almost-
Empty and Almost-Full flags
• Program programmable flags by either serial or parallel means
• Select IDT Standard timing (using EF and FF flags) or First Word
Fall Through timing (using OR and IR flags)
• Output enable puts data outputs into high impedance state
• Easily expandable in depth and width
• JTAG port, provided for Boundary Scan function (PBGA Only)
• Independent Read and Write Clocks (permit reading and writing
simultaneously)
• Available in a 128-pin Thin Quad Flat Pack (TQFP) or a 144-pin Plastic
Ball Grid Array (PBGA) (with additional features)
• Pin compatible to the SuperSync II (IDT72V3640/72V3650/72V3660/
72V3670/72V3680/72V3690) family
• High-performance submicron CMOS technology
• Industrial temperature range (–40°C to +85°C) is available
* WEN WCLK/WR
D0 -Dn (x36, x18 or x9)
LD SEN
*ASYW
WRITE CONTROL
LOGIC
WRITE POINTER
INPUT REGISTER
RAM ARRAY
65,536 x 36
131,072 x 36
OFFSET REGISTER
FLAG
LOGIC
READ POINTER
FF/IR
PAF
EF/OR
PAE
HF
FWFT/SI
PFM
FSEL0
FSEL1
BE
IP
BM
IW
OW
MRS
PRS
CONTROL
LOGIC
BUS
CONFIGURATION
RESET
LOGIC
OUTPUT REGISTER
READ
CONTROL
LOGIC
TCK
*TRST
* TMS
* TDI
**TDO
JTAG CONTROL
(BOUNDARY
SCAN)
*
OE
Q0 -Qn (x36, x18 or x9)
IDT and the IDT logo are a registered trademarks of Integrated Device Technology, Inc. The SuperSync II FIFO is a trademark of Integrated Device Technology, Inc.
COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGES
1
2003 Integrated Device Technology, Inc. All rights reserved. Product specifications subject to change without notice.
RT
RM
* ASYR
* RCLK/RD
REN
6117 drw01
SEPTEMBER 2003
DSC-6117/10
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