IDT72V3611(2014) Просмотр технического описания (PDF) - Integrated Device Technology
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IDT72V3611 Datasheet PDF : 19 Pages
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IDT72V3611 3.3V, CMOS SyncFIFOTM
64 x 36
COMMERCIAL TEMPERATURE RANGE
is LOW and from the mail1 register when MBB is HIGH. Mail2 data is always
present on the port-A data (A0-A35) outputs when they are active. The Mail1
Register Flag (MBF1) is set HIGH by a LOW-to-HIGH transition on CLKB when
a port-B read is selected by CSB, W/RB, and ENB with MBB HIGH. The Mail2
Register Flag (MBF2) is set HIGH by a LOW-to-HIGH transition on CLKA when
a port-A read is selected by CSA, W/RA, and ENA with MBA HIGH. The data
in a mail register remains intact after it is read and changes only when new data
is written to the register. For relevant mail register and mail register flag timing
diagrams, see Figure 9 and Figure 10.
PARITY CHECKING
The port-A (A0-A35) inputs and port-B (B0-B35) inputs each have four
parity trees to check the parity of incoming (or outgoing) data. A parity failure
on one or more bytes of the input bus is reported by a LOW level on the port
Parity Error Flag (PEFA, PEFB). Odd or even parity checking can be selected,
and the Parity Error Flags can be ignored if this feature is not desired.
Parity status is checked on each input bus according to the level of the Odd/
Even parity (ODD/EVEN) select input. A parity error on one or more bytes
of a port is reported by a LOW level on the corresponding port Parity Error Flag
(PEFA, PEFB) output. Port-A bytes are arranged as A0-A8, A9-A17, A18-
A26, and A27-A35, and port-B bytes are arranged as B0-B8, B9-B17, B18-
B26, and B27-B35. When Odd/Even parity is selected, a port Parity Error Flag
(PEFA, PEFB) is LOW if any byte on the port has an odd/even number of LOW
levels applied to its bits.
The four parity trees used to check the A0-A35 inputs are shared by the
mail2 register when parity generation is selected for port-A reads
(PGA=HIGH). When port-A read from the mail2 register with parity generation
is selected with CSA LOW, ENA HIGH, W/RA LOW, MBA HIGH, and PGA
HIGH, the port-A Parity Error Flag (PEFA) is held HIGH regardless of the levels
applied to the A0-A35 inputs. Likewise, the parity trees used to check the B0-
B35 inputs are shared by the mail1 register when parity generation is selected
for port-B reads (PGB=HIGH). When a port-B read from the mail1 register with
parity generation is selected with CSB LOW, ENB HIGH, W/RB LOW, MBB
HIGH, and PGB HIGH, the port-B Parity Error Flag (PEFB) is held HIGH
regardless of the levels applied to the B0-B35 inputs.
PARITY GENERATION
A HIGH level on the port-A Parity Generate select (PGA) or port-B Parity
Generate select (PGB) enables the IDT72V3611 to generate parity bits for
port reads from a FIFO or mailbox register. Port-A bytes are arranged as A0-
A8, A9-A17, A18-A26, and A27-A35, with the most significant bit of each byte
used as the parity bit. Port-B bytes are arranged as B0-B8, B9-B17, B18-B26,
and B27-B35, with the most significant bit of each byte used as the parity bit. A
write to a FIFO or mail register stores the levels applied to all thirty-six inputs
regardless of the state of the Parity Generate select (PGA, PGB) inputs. When
data is read from a port with parity generation selected, the lower eight bits of
each byte are used to generate a parity bit according to the level on the ODD/
EVEN select. The generated parity bits are substituted for the levels originally
written to the most significant bits of each byte as the word is read to the data
outputs.
Parity bits for FIFO data are generated after the data is read from the FIFO
RAM and before the data is written to the output register. Therefore, the port-
B Parity Generate select (PGB) and ODD/EVEN have setup and hold time
constraints to the port-B clock (CLKB) for a rising edge of CLKB used to read
a new word to the FIFO output register.
The circuit used to generate parity for the mail1 data is shared by the port-
B bus (B0-B35) to check parity and the circuit used to generate parity for the
mail2 data is shared by the port-A bus (A0-A35) to check parity. The shared
parity trees of a port are used to generate parity bits for the data in a mail register
when the port Write/Read select (W/RA, W/RB) input is LOW, the port Mail select
(MBA, MBB) input is HIGH, Chip Select (CSA, CSB) is LOW, Enable (ENA,
ENB) is HIGH, and the port Parity Generate select (PGA, PGB) is HIGH.
Generating parity for mail register data does not change the contents of the
register (see Figure 13 and Figure 14).
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