IDT72105 Просмотр технического описания (PDF) - Integrated Device Technology

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IDT72105

CMOS PARALLEL-TO-SERIAL FIFO 256 x 16, 512 x 16, 1024 x 16

Integrated Device Technology 

IDT72105, IDT72115, IDT72125,

256 x 16, 512 x 16, 1024 x 16 PARALLEL-TO-SERIAL CMOS FIFO

DATA IN

COMMERCIAL TEMPERATURE RANGE

W

t WEF

t SOCEF

EF

SOCP

NOTE 1

t REFSO

0

1

n–1

NOTE 2

t SOLZ

SO

NOTE:

t SOPD

1. Once EF has gone LOW and the last bit of the final word has been shifted out, SOCP should not be clocked until EF goes HIGH.

2. In Single Device Mode, SO will not tri-state except after Reset. It will retain the last valid data.

Figure 6. Empty Boundary Condition Timing

2665 drw 09

SOCP

0

t SOCFF

1

n–1

t WFF

FF

t WPF

W

t DS

t DH

DATA IN

NOTE 1

t SOPD

DATA IN VALID

SO

DATA OUT VALID

NOTE:

1. Single Device Mode will not tri-state but will retain the last valid data.

Figure 7. Full Boundary Condition Timing

NOTE 1

2665 drw 10

W

HALF-FULL (1/2)

HF

SOCP

AEF

7/8 FULL

t WF

t WF

AEF

ALMOST-EMPTY

(1/8 FULL – 1)

HALF-FULL + 1

ALMOST-FULL (7/8 FULL + 1)

1/8 FULL

t SOCF

t SOCF

Figure 8. Half-Full, Almost-Full and Almost-Empty Timings

HALF-FULL

7/8 FULL

ALMOST-EMPTY

(1/8 FULL – 1)

2665 drw 11

5.35

7

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