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IDT72105

CMOS PARALLEL-TO-SERIAL FIFO 256 x 16, 512 x 16, 1024 x 16

Integrated Device Technology 

IDT72105, IDT72115, IDT72125,

256 x 16, 512 x 16, 1024 x 16 PARALLEL-TO-SERIAL CMOS FIFO

AC TEST CONDITIONS

Input Pulse Levels

Input Rise/Fall Times

Input Timing Reference Levels

Output Reference Levels

Output Load

GND to 3.0V

5ns

1.5V

1.5V

See Figure A

2665 tbl 07

CAPACITANCE (TA = +25°C, f = 1.0MHz)

Symbol

Parameter(1)

Conditions Max. Unit

CIN

Input Capacitance

VIN = 0V

10 pF

COUT

Output

Capacitance

VOUT = 0V

12 pF

NOTE:

1. This parameter is sampled and not 100% tested.

2665 tbl 08

COMMERCIAL TEMPERATURE RANGE

TO

OUTPUT

PIN

680Ω

5V

1.1KΩ

30pF*

2665 drw 03

or equivalent circuit

Figure A. Output Load

*Includes jig and scope capacitances.

FUNCTIONAL DESCRIPTION

Parallel Data Input

The device must be reset before beginning operation so

that all flags are set to their initial state. In width or depth

expansion the First Load pin (FL) must be programmed to

indicate the first device.

The data is written into the FIFO in parallel through the D0–

15 input data lines. A write cycle is initiated on the falling edge

of the Write (W) signal provided the Full Flag (FF) is not

asserted. If the W signal changes from HIGH-to-LOW and the

Full Flag (FF) is already set, the write line is internally inhibited

internally from incrementing the write pointer and no write

operation occurs.

Data set-up and hold times must be met with respect to the

rising edge of Write. On the rising edge of W, the write pointer

is incremented. Write operations can occur simultaneously or

asynchronously with read operations.

Serial Data Output

The serial data is output on the SO pin. The data is clocked

out on the rising edge of SOCP providing the Empty Flag (EF)

is not asserted. If the Empty Flag is asserted then the next data

word is inhibited from moving to the output register and being

clocked out by SOCP.

The serial word is shifted out Least Significant Bit or Most

Significant Bit first, depending on the FL/DIR level during

operation. A LOW on DIR will cause the Least Significant Bit

to be read out first. A HIGH on DIR will cause the Most

Significant Bit to be read out first.

RS

W

AEF, EF

HF, FF

SOCP

FL/DIR

tRSC

tRS

tRSS

tRSC

tRSC

tRSS

NOTE 2

tFLS

tRSR

tRSR

tFLH

NOTES:

1. EF, FF, HF and AEF may change status during Reset, but flags will be valid at tRSC.

2. SOCP should be in the steady LOW or HIGH during tRSS. The first LOW-HIGH (or HIGH-LOW) transition can begin after tRSR.

Figure 1. Reset

FLAG

STABLE

FLAG

STABLE

2665 drw 04

5.35

5

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