IDT72105 Просмотр технического описания (PDF) - Integrated Device Technology

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производитель

IDT72105

CMOS PARALLEL-TO-SERIAL FIFO 256 x 16, 512 x 16, 1024 x 16

Integrated Device Technology 

IDT72105, IDT72115, IDT72125,

256 x 16, 512 x 16, 1024 x 16 PARALLEL-TO-SERIAL CMOS FIFO

LOW AT RESET

PARALLEL DATA IN

ADDRESS 00

DECODER 01

74FCT138 10

D 0–15

W

SOCP

RSIX

FL/DIR EF

FIFO #1

HF

RSOX

SO FF

HIGH AT RESET

SERIAL OUTPUT CLOCK

D 0–15

W

SOCP

RSIX

FL/DIR EF

FIFO #2

HF

RSOX

SO FF

COMMERCIAL TEMPERATURE RANGES

EMPTY

FLAG

HALF-FULL

FLAG

D 0–15

W

SOCP

HIGH AT RESET

RSIX

FL/DIR EF

FIFO #3

HF

RSOX

SO FF

Figure 12. A 3K x 16 Parallel-to-Serial FIFO using the IDT72125

FULL

FLAG

SERIAL DATA OUT

2665 drw 15

Mode

Inputs

RS

FL

DIR

Internal Status

Read Pointer

Write Pointer

Outputs

EF

HF, FF

Reset-First Device

0

0

X

Location Zero

Location Zero

0

1

Reset All Other Devices

0

1

X

Location Zero

Location Zero

0

1

Read/Write

1

X

0,1

X

X

X

X

NOTE:

1. RS = Reset Input, FL/FIR = First Load/Direction, EF = Empty Flag Output, HF = Half- Full Flag Output, FF = Full Flag Output.

2665 tbl 10

Table 2. Reset and First Load Truth Table–Width/Depth Compound Expansion Mode

5.35

10

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