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IDT7164L15PG Просмотр технического описания (PDF) - Integrated Device Technology

Номер в каталоге
Компоненты Описание
производитель
IDT7164L15PG
IDT
Integrated Device Technology IDT
IDT7164L15PG Datasheet PDF : 11 Pages
1 2 3 4 5 6 7 8 9 10
IDT7164S/L
CMOS Static RAM 64K (8K x 8-Bit)
Military, Commercial, and Industrial Temperature Ranges
AC Electrical Characteristics (con't.) (VCC = 5.0V ± 10%, Military Temperature Ranges)
Symbol
Parameter
7164S45
7164L45
Min. Max.
7164S55
7164L55
Min. Max.
7164S70
7164L70
Min. Max.
7164S85/100
7164L85/100
Min. Max. Unit
Read Cycle
tRC
Read Cycle Time
tAA
Address Access Time
tACS1(1) Chip Select-1 Access Time
tACS2(1) Chip Select-2 Access Time
45
____
55
____
70
____
85/100
____
ns
____
45
____
55
____
70
____ 85/100 ns
____
45
____
55
____
70
____ 85/100 ns
____
45
____
55
____
70
____ 85/100 ns
tCLZ1,2(2)
tOE
tOLZ(2)
Chip Select-1, 2 to Output in Low-Z
Output Enable to Output Valid
Output Enab le to Output in Low-Z
5
____
5
____
5
____
5
____
ns
____
25
____
30
____
35
____
40 ns
0
____
0
____
0
____
0
____
ns
tCHZ1,2(2) Chip Select-1,2 to Output in High-Z
____
20
____
25
____
30
____
35 ns
tOHZ(2)
tOH
tPU(2)
tPD(2)
Output Disab le to Output in High-Z
Output Hold from Address Change
Chip Sele ct to Power Up Time
Chip Deselect to Power Down Time
____
20
____
25
____
30
____
35 ns
5
____
5
____
5
____
5
____
ns
0
____
0
____
0
____
0
____
ns
____
45
____
55
____
70
____ 85/100 ns
Write Cycle
tWC
Write Cycle Time
45
____
55
____
70
____
85/100
____
ns
tCW1,2 Chip Select to End-of-Write
33
____
50
____
60
____
75
____
ns
tAW
Address Valid to End-of-Write
33
____
50
____
60
____
75
____
ns
tAS
Address Set-up Time
0
____
0
____
0
____
0
____
ns
tWP
Write Pulse Width
tWR1
Write Recovery Time (CS1, WE)
25
____
50
____
60
____
75
____
ns
0
____
0
____
0
____
0
____
ns
tWR2
Write Recovery Time (CS2)
5
____
5
____
5
____
5
____
ns
tWHZ(2)
Write Enab le to Output in High-Z
____
18
____
25
____
30
____
35 ns
tDW
Data to Write Time Overlap
tDH1
Data Hold from Write Time (CS1, WE)
20
____
25
____
30
____
35
____
ns
0
____
0
____
0
____
0
____
ns
tDH2
Data Hold from Write Time (CS2)
5
____
5
____
5
____
5
____
ns
tOW(2)
Output Active from End-of-Write
4
____
4
____
4
____
4
____
ns
NOTES:
1. Both chip selects must be active for the device to be selected.
2. This parameter is guaranteed by device characterization, but is not production tested.
2967 tbl 13
6

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