HFA1149EVAL Просмотр технического описания (PDF) - Intersil
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HFA1149EVAL Datasheet PDF : 13 Pages
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HFA1149
PC Board Layout
The frequency response of this amplifier depends greatly on
the care taken in designing the PC board. The use of low
inductance components such as chip resistors and chip
capacitors is strongly recommended, while a solid
ground plane is a must! Attention should be given to
decoupling the power supplies. A large value (10µF)
tantalum in parallel with a small value (0.1µF) chip capacitor
works well in most cases.
Terminated microstrip signal lines are recommended at the
input and output of the device. Capacitance directly on the
output must be minimized, or isolated as discussed in the
next section.
Care must also be taken to minimize the capacitance to
ground seen by the amplifier’s inverting input (-IN). The
larger this capacitance, the worse the gain peaking, resulting
in pulse overshoot and possible instability. Thus, it is
recommended that the ground plane be removed under
traces connected to -IN, and connections to -IN should be
kept as short as possible.
Driving Capacitive Loads
Capacitive loads, such as an A/D input, or an improperly
terminated transmission line will degrade the amplifier’s
phase margin resulting in frequency response peaking and
possible oscillations. In most cases, the oscillation can be
avoided by placing a resistor (RS) in series with the output
prior to the capacitance.
RS and CL form a low pass network at the output, thus
limiting system bandwidth well below the amplifier
bandwidth. By decreasing RS as CL increases, the
maximum bandwidth is obtained without sacrificing stability.
In spite of this, bandwidth still decreases as the load
capacitance increases.
Evaluation Board
The performance of the HFA1149 may be evaluated using
the HFA11XX Evaluation Board (part number
HFA11XXEVAL). Please contact your local sales office for
information. When evaluating this amplifier, the two 510Ω
gain setting resistors on the evaluation board should be
changed to 250Ω.
The layout and schematic of the board are shown in Figure 2.
NOTE: The SOIC version may be evaluated in the DIP board by
using a SOIC-to-DIP adapter such as Aries Electronics Part Number
08-350000-10.
.
510Ω
50Ω
IN
10µF 0.1µF
BOARD SCHEMATIC
510Ω
VH
1
8
0.1µF
10µF
2
7
+5V
50Ω
3
6
OUT
4
5
VL
GND
-5V
GND
TOP LAYOUT
VH
1
+IN
OUT V+
VL V-
GND
BOTTOM LAYOUT
FIGURE 2. EVALUATION BOARD SCHEMATIC AND LAYOUT
6
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