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HFA1149EVAL Datasheet PDF : 13 Pages
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HFA1149
Application Information
Optimum Feedback Resistor
Although a current feedback amplifier’s bandwidth
dependency on closed loop gain isn’t as severe as that of a
voltage feedback amplifier, there can be an appreciable
decrease in bandwidth at higher gains. This decrease may
be minimized by taking advantage of the current feedback
amplifier’s unique relationship between bandwidth and RF.
All current feedback amplifiers require a feedback resistor,
even for unity gain applications, and RF, in conjunction with
the internal compensation capacitor, sets the dominant pole
of the frequency response. Thus, the amplifier’s bandwidth is
inversely proportional to RF. The HFA1149 design is
optimized for a 250Ω RF at a gain of +2. Decreasing RF
decreases stability, resulting in excessive peaking and
overshoot (Note: Capacitive feedback will cause the same
problems due to the feedback impedance decrease at higher
frequencies). At higher gains the amplifier is more stable, so
RF can be decreased in a trade-off of stability for bandwidth.
TABLE 1. OPTIMUM FEEDBACK RESISTOR
GAIN
(ACL)
-1
RF (Ω)
200
BANDWIDTH (MHz)
375
+1
250 (+RS = 700Ω)
330
+2
250
450
+5
100
160
+10
90
70
Table 1 lists recommended RF values, and the expected
bandwidth, for various closed loop gains. For a gain of +1, a
resistor (+RS) in series with +IN is required to reduce gain
peaking and increase stability
Output Disable Function
The HFA1149 incorporates an output disable function that is
useful for reducing power dissipation or for multiplexing
signals onto a common analog bus. When disabled, the
inverting input and the output become high impedances
(however, the feedback network for gains other than +1 still
present a load to ground from the output), the supply current
reduces by 68%, and the input to output isolation becomes
greater than 60dB. The amplifier is disabled by driving the
DIS / DIS input to its active state.
The active state of the DIS / DIS input is user programmable
via the HFA1149’s Polarity Set input (see next paragraph). If
the Polarity Set input is left floating, or is tied to a logic high
(e.g., V+), then the disable function is activated by a logic
low on the DIS / DIS input (typical of most output disable op
amps). If the Polarity Set input is connected to a logic low
(e.g., GND), then a logic high on the DIS / DIS input disables
the amplifier.
The DIS / DIS input is TTL compatible, and unlike most
competitive devices, the TTL compatibility can be
maintained when the HFA1149 is operated at supplies other
than ±5V (see the “Threshold Set input” section below).
An internal resistive bias network ensures that the DIS / DIS
pin is pulled high if it is undriven on the PCB.
Polarity Set Input
A novel feature of the HFA1149 is the polarity
programmability of the disable control pin (DIS / DIS).
Depending on the state of the Polarity Set input (pin 5), the
designer can define the active state to be high or low for the
DIS / DIS input (see the “HFA1149 Disable Functionality”
table on the front page). With this feature, a 2:1 multiplexer
can be created by defining one amplifier’s disable control as
active low (Polarity Set = High or floating), and the other
amplifier’s control as active high (Polarity Set = Low). Note
that if the Polarity Set pin is left floating, an internal pull-up
resistor pulls the pin high, and the HFA1149 becomes a
drop-in replacement for any standard ±5V supply op amp
with output disable (e.g., CLC410, CLC411, CLC430,
HA-5020, HFA1145, AD810). Likewise, if the disable and
polarity set pins are both floated, the HFA1149 works just
like a standard op amp (i.e., the output is always enabled).
Threshold Set Input for TTL Compatibility
The HFA1149 derives an internal threshold reference for the
digital circuitry as long as the power supplies are nominally
±5V. This reference is used to ensure the TTL compatibility
of the DIS / DIS and Polarity Set inputs. With symmetrical
±5V supplies the Threshold Set pin (Pin 1) must be floated to
guarantee TTL compatibility. If asymmetrical supplies (e.g.,
+10V, 0V) are utilized, and TTL compatibility is desired, the
Threshold Set pin must be connected to an external voltage
(e.g., GND for +10V, 0V operation). The following equation
should be used to determine the voltage (VTHSET) to be
applied to the Threshold Set pin:
VTHSET = 1.58(VDIGTH + 1.6V) – V--8---- – 0.46(V+),
where VDIGTH is the desired switching point (typically 1.4V
for TTL compatibility) of the Polarity Set and DIS / DIS
inputs.
Figure 1 illustrates the input impedance of the Threshold Set
pin for calculating the input current at a given VTHSET.
V+
7kΩ
3kΩ
VTHSET
25kΩ
V-
FIGURE 1. THRESHOLD SET INPUT IMPEDANCE
5
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