IDT54FCT833A Просмотр технического описания (PDF) - Integrated Device Technology
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IDT54FCT833A Datasheet PDF : 8 Pages
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IDT54/74FCT833A/B
FAST CMOS PARITY BUS TRANSCEIVER
PIN CONFIGURATIONS
OER
R0
R1
R2
R3
R4
R5
R6
R7
ERR
CLR
GND
1
24
2
23
3
22
4 P24-1, 21
5 D24-1, 20
6
S024-2
&
19
7 E24-1 18
8
17
9
16
10
15
11
14
12
13
Vcc
T0
T1
T2
T3
T4
T5
T6
T7
PARITY
OET
CLK
DIP/SOIC/CERPACK
TOP VIEW
MILITARY AND COMMERCIAL TEMPERATURE RANGES
INDEX
4 3 2 28 27 26
R2 5
R3 6
1
25 T2
24 T3
R4 7
NC 8
L28-1
23 T4
22 NC
R5 9
21 T5
R6 10
20 T6
R7 11
19 T7
12 13 14 15 16 17 18
LCC
TOP VIEW
2557 drw 02
PIN DESCRIPTION
Pin Name I/O
Description
OER
I RECEIVE enable input.
RI
I/O 8-bit RECEIVE data input/output.
ERR
O Output from fault registers. Register
detection of odd parity fault on rising clock
edge (CLK). A registered ERR output
remains LOW until cleared. Open drain
output, requires pull up resistor.
CLR
I Clears the fault register output.
TI
I/O 8-bit TRANSMIT data input/output.
PARITY
OET
I/O 1-bit PARITY output.
I TRANSMIT enable input.
CLK
I External clock pulse input for fault register
flag.
2557 tbl 01
ERROR FLAG OUTPUT FUNCTION TABLE(1,2)
Internal Output
Inputs To Device Pre-State
CLR CLK Point “P” ERRn–1
Output
ERR
Function
H
↑
H
H
↑
—
H
↑
L
H
H
Sample
L
L
(1’s
—
L
Capture)
L
—
—
—
H
Clear
NOTES:
1. OET is HIGH and OER is LOW.
2. H = HIGH
L = LOW
↑ = LOW-to-HIGH transition of clock
– = Don't Care or Irrelevant
2557 tbl 02
7.21
2
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