IDT49FCT805APYG Просмотр технического описания (PDF) - Integrated Device Technology
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IDT49FCT805APYG Datasheet PDF : 7 Pages
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IDT49FCT805/A
FAST CMOS BUFFER/CLOCK DRIVER
TEST CIRCUITS AND WAVEFORMS
VCC
7V
VIN
Pulse
Generator
500
VOUT
D.U.T.
50pF
RT
500
CL
IN P U T
OUTPUT
IN P U T
OUTPUT
Test Circuits for All Outputs
tPLH
tPHL
tR
tF
Package Delay
3V
1.5V
0V
VOH
2.0V
1.5V
0.8V
VOL
tPLH
tPHL
tSK(p) = tPHL - tPLH
Pulse Skew - tSK(P)
3V
1.5V
0V
VOH
1.5V
VOL
CONTROL
INPUT
OUTPUT
NORMALLY
LOW
OUTPUT
NORMALLY
HIGH
ENABLE
tPZL
SW ITC H
CLOSED
tPZH
3.5V
1.5V
SW ITCH
OPEN
1.5V
0V
D IS A B L E
tPLZ
3V
1.5V
0V
tPHZ
3.5V
0.3V VOL
0.3V VOH
0V
Enable and Disable Times
NOTES:
1. Diagram shown for input Control Enable-LOW and input Control Disable-HIGH
2. Pulse Generator for All Pulses: Rate ≤1.0MHz; tF ≤2.5ns; tR ≤2.5ns
COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGE
SWITCH POSITION
Test
Disable LOW
Enable LOW
Disable HIGH
Enable HIGH
Switch
Closed
GND
DEFINITIONS:
CL = Load capacitance: includes jig and probe capacitance.
RT = Termination resistance: should be equal to ZOUT of the Pulse Generator.
IN P U T
OUTPUT 1
OUTPUT 2
tPLH1
tPLH1
tS K (o )
tS K (o )
tPLH2
tPHL2
tSK(o) = tPLH2 - tPLH1 or tPHL2 - tPHL1
Output Skew
3V
1.5V
0V
VOH
1.5V
VOL
VOH
1.5V
VOL
IN P U T
tPLH1
tPHL1
PACKAGE 1
OUTPUT
PACKAGE 2
OUTPUT
tS K (p p )
tSK(pp)
tPLH2
tPHL2
tSK(pp) = tPLH2 - tPLH1 or tPHL2 - tPHL1
Part-to-Part Skew - tSK(PP)
3V
1.5V
0V
VOH
1.5V
VOL
VOH
1.5V
VOL
NOTE:
1. Package 1 and Package 2 are same device type and speed grade.
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