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IDT2308A-2PG

3.3V ZERO DELAY CLOCK MULTIPLIER

Integrated Device Technology 

IDT2308A

3.3V ZERO DELAY CLOCK MULTIPLIER

COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGES

FUNCTION TABLE(1) SELECT INPUT DECODING

S2

S1

CLK A

CLK B

L

L

Tri-State

Tri-State

L

H

Driven

Tri-State

H

L

Driven

Driven

H

H

Driven

Driven

NOTE:

1. H = HIGH Voltage Level

L = LOW Voltage Level

Output Source

PLL

PLL

REF

PLL

PLL Shut Down

Y

N

Y

N

AVAILABLE OPTIONS FOR IDT2308A

Device

Feedback From

IDT2308A-1

Bank A or Bank B

IDT2308A-1H

Bank A or Bank B

IDT2308A-2

Bank A

IDT2308A-2

Bank B

IDT2308A-2H

Bank A

IDT2308A-2H

Bank B

IDT2308A-3

Bank A

IDT2308A-3

Bank B

IDT2308A-4

Bank A or Bank B

NOTE:

1. Output phase is indeterminant (0° or 180° from input clock).

Bank A Frequency

Reference

Reference

Reference

2 x Reference

Reference

2 x Reference

2 x Reference

4 x Reference

2 x Reference

Bank B Frequency

Reference

Reference

Reference/2

Reference

Reference/2

Reference

Reference or Reference(1)

2 x Reference

2 x Reference

ZERO DELAY AND SKEW CONTROL

To close the feedback loop of the IDT2308A, the FBK pin can be driven from any of the eight available output pins. The output driving the FBK pin

will be driving a total load of 7pF plus any additional load that it drives. The relative loading of this output (with respect to the remaining outputs) can adjust

the input-output delay.

For applications requiring zero input-output delay, all outputs including the one providing feedback should be equally loaded. Ensure the outputs are

loaded equally, for zero output-output skew.

3

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