ICS853031 Просмотр технического описания (PDF) - Integrated Circuit Systems

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ICS853031

LOW SKEW, 1-TO-9 DIFFERENTIAL-TO-2.5V/3.3V LVPECL/ECL FANOUT BUFFER

Integrated Circuit Systems 

Integrated

Circuit

Systems, Inc.

ICS853031

LOW SKEW, 1-TO-9

DIFFERENTIAL-TO-2.5V/3.3V LVPECL/ECL FANOUT BUFFER

APPLICATION INFORMATION

WIRING THE DIFFERENTIAL INPUT TO ACCEPT SINGLE ENDED LEVELS

Figure 2 shows how the differential input can be wired to accept

single ended levels. The reference voltage V_REF ~ VCC/2 is

generated by the bias resistors R1, R2 and C1. This bias circuit

should be located as close as possible to the input pin. The ratio

of R1 and R2 might need to be adjusted to position the V_REF in

the center of the input voltage swing. For example, if the input

clock swing is only 2.5V and V = 3.3V, V_REF should be 1.25V

CC

and R2/R1 = 0.609.

VCC

CLK_IN

C1

0.1uF

R1

1K

+

V_REF

-

R2

1K

FIGURE 2. SINGLE ENDED SIGNAL DRIVING DIFFERENTIAL INPUT

TERMINATION FOR 3.3V LVPECL OUTPUTS

The clock layout topology shown below is a typical termina-

tion for LVPECL outputs. The two different layouts mentioned

are recommended only as guidelines.

FOUT and nFOUT are low impedance follower outputs that

generate ECL/LVPECL compatible outputs.Therefore, terminat-

ing resistors (DC current path to ground) or current sources

must be used for functionality. These outputs are designed to

drive 50Ω transmission lines. Matched impedance techniques

should be used to maximize operating frequency and minimize

signal distortion. Figures 3A and 3B show two different layouts

which are recommended only as guidelines. Other suitable clock

layouts may exist and it would be recommended that the board

designers simulate to guarantee compatibility across all printed

circuit and clock component process variations.

Zo = 50Ω

FOUT

FIN

Zo = 50Ω

50Ω

RTT =

1

((VOH + VOL) / (VCC – 2)) – 2

Zo

50Ω

VCC - 2V

RTT

FOUT

3.3V

125Ω

125Ω

Zo = 50Ω

FIN

Zo = 50Ω

84Ω

84Ω

FIGURE 3A. LVPECL OUTPUT TERMINATION

FIGURE 3B. LVPECL OUTPUT TERMINATION

853031AY

www.icst.com/products/hiperclocks.html

REV. B SEPTEMBER 16, 2004

9

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