ICS853001 Просмотр технического описания (PDF) - Integrated Circuit Systems
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ICS853001 Datasheet PDF : 16 Pages
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Integrated
Circuit
Systems, Inc.
ICS853001
1:1, DIFFERENTIAL LVPECL-TO-
2.5V, 3.3V, 5V LVPECL/ECL BUFFER
GENERAL DESCRIPTION
The ICS853001 is a 1:1 Differential LVPECL-
ICS
to-LVPE C L B u f fe r a n d a m e m b e r o f t h e
HiPerClockS™ HiPerClock S ™family of High Perfor mance
Clock Solutions from ICS. The ICS853001
may be used to regenerate LVPECL clocks which
may have been attenuated, across a long trace, or may also
be used as a differential-to-LVPECL translator. The differen-
tial input can accept the following differential input types:
LVPECL, LVDS and CML. The device also has an output en-
able pin for debug/test purposes. When the output is disabled,
it drives differential LOW (Q = LOW, nQ = HIGH). The
ICS853001 is packaged in either a 3mm x 3mm 8-pin TSSOP
or 3.9mm x 4.9mm 8-pin SOIC, making it ideal for use on
space-constrained boards.
FEATURES
• 1:1 Differential LVPECL-to-LVPECL / ECL buffer
• 1 LVPECL clock output pair
• 1 Differential LVPECL PCLK, nPCLK input pair
• PCLK, nPCLK pair can accept the following
differential input levels: LVPECL, LVDS, CML
• Maximum output frequency: >2.5GHz
• Part-to-part skew: 100ps (maximum)
• Propagation delay: 500ps (maximum)
• Additive phase jitter, RMS: 0.03ps (typical)
• LVPECL mode operating voltage supply range:
V = 2.375V to 5.25V, V = 0V
CC
EE
• ECL mode operating voltage supply range:
V = 0V, V = -5.25V to -2.375V
CC
EE
• -40°C to 85°C ambient operating temperature
• Lead-Free package RoHS compliant
BLOCK DIAGRAM
OE
DQ
LE
PCLK
nPCLK
V
BB
853001AG
PIN ASSIGNMENT
VCC 1
8 OE
Q2
7 PCLK
nQ 3
VEE 4
6 nPCLK
5 VBB
Q
ICS853001
nQ
8-Lead TSSOP, 118 mil
3mm x 3mm x 0.95mm package body
G Package
Top View
ICS853001
8-Lead SOIC
3.90mm x 4.90mm x 1.37mm package body
M Package
Top View
www.icst.com/products/hiperclocks.html
1
REV. A JANUARY 29, 2005
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