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ICS81006AKIT

VCXO-TO-LVCMOS OUTPUTS

Integrated Device Technology 

ICS81006I

VCXO-TO-6 LVCMOS OUTPUTS

TABLE 6. VARACTOR PARAMETERS

Symbol

CV_LOW

CV_HIGH

Parameter

Low Varactor Capacitance

High Varactor Capacitance

Test Conditions

VC = 0V

VC = 3.3V

Minimum

Typical

15.4

29.6

Maximum

Units

pF

pF

FORMULAS

(( )) (( )) CLow =

CL1 + CS1 + CV _ Low ⋅ CL2 + CS 2 + CV _ Low

CL1 + CS1 + CV _ Low + CL2 + CS 2 + CV _ Low

(( )) (( )) CHigh =

CL1 + CS1 + CV _ High ⋅ CL2 + CS 2 + CV _ High

CL1 + CS1 + CV _ High + CL2 + CS 2 + CV _ High

• C is the effective capacitance due to the low varactor capacitance, load capacitance and stray capacitance.

Low

CLow determines the high frequency component on the TPR.

• CHigh is the effective capacitance due to the high varactor capacitance, load capacitance and stray capacitance.

CHigh determines the low frequency component on the TPR.





Total

Pull

Range (TPR)

=



1







2

⋅

C

0

C1

⋅

1

+

C

Low

C 0 

−

1

2

⋅

C

0

C1

⋅

1



+

C

High

C

0













⋅

10

6

Absolute Pull Range (APR) = Total Pull Range – (Frequency Tolerance + Frequency Stability + Aging)

EXAMPLE CALCULATIONS

Using the tables and figures above, we can now calculate the

TPR and APR of the VCXO using the example crystal parameters.

For the numerical example below there were some assumptions

made. First, the stray capacitance (C , C ), which is all the excess

S1 S2

capacitance due to board parasitic, is 4pF. Second, the expected

lifetime of the project is 5 years; hence the inaccuracy due to

CLow

=

(0 + 4 pf

(0 + 4 pf

+15.4 pf )⋅ (0 + 4 pf

+15.4 pf ) + (0 + 4 pf

+15.4 pf )

+15.4 pf )

=

9.7

pf

aging is ±15ppm. Third, though many boards will not require load

tuning capacitors (CL1, CL2), it is recommended for long-term

consistent performance of the system that two tuning capacitor

pads be placed into every design.Typical values for the load tuning

capacitors will range from 0 to 4pF.

CHigh

=

(0 + 4 pf

(0 + 4 pf

+ 29.6 pf )⋅ (0 + 4 pf

+ 29.6 pf ) + (0 + 4 pf

+ 29.6 pf )

+ 29.6 pf )

= 16.8 pf



TPR = 

1

−

1



 ⋅ 106 ⋅ = 226.5 ppm

 2 ⋅ 220 ⋅ 1+ 9.7 pF 4 pF  2 ⋅ 220 ⋅ 1 +16.8 pF 4 pF  

TPR = ±113.25ppm

APR = 113.25ppm – (20ppm + 20ppm + 15ppm) = ±58.25ppm

The example above will ensure a total pull range of

±113.25 ppm with an APR of ±58.25ppm. Many times, board

designers may select their own crystal based on their

application. If the application requires a tighter APR, a crystal

with better pullability (C0/C1 ratio) can be used. Also, with the

equations above, one can vary the frequency tolerance,

temperature stability, and aging or shunt capacitance to achieve

the required pullability.

IDT™ / ICS™ VCXO-TO-LVCMOS OUTPUTS

9

ICS81006AKI REV A OCTOBER 2, 2006

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