HGTG11N120CND Просмотр технического описания (PDF) - Fairchild Semiconductor
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HGTG11N120CND
Fairchild Semiconductor
HGTG11N120CND Datasheet PDF : 8 Pages
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HGTG11N120CND
Test Circuit and Waveforms
HGTG11N120CND
RG = 10Ω
L = 2mH
+
VDD = 960V
-
FIGURE 20. INDUCTIVE SWITCHING TEST CIRCUIT
Handling Precautions for IGBTs
Insulated Gate Bipolar Transistors are susceptible to
gate-insulation damage by the electrostatic discharge of
energy through the devices. When handling these devices,
care should be exercised to assure that the static charge built
in the handler’s body capacitance is not discharged through
the device. With proper handling and application procedures,
however, IGBTs are currently being extensively used in
production by numerous equipment manufacturers in military,
industrial and consumer applications, with virtually no damage
problems due to electrostatic discharge. IGBTs can be
handled safely if the following basic precautions are taken:
1. Prior to assembly into a circuit, all leads should be kept
shorted together either by the use of metal shorting
springs or by the insertion into conductive material such as
“ECCOSORBD™ LD26” or equivalent.
2. When devices are removed by hand from their carriers, the
hand being used should be grounded by any suitable
means - for example, with a metallic wristband.
3. Tips of soldering irons should be grounded.
4. Devices should never be inserted into or removed from
circuits with power on.
5. Gate Voltage Rating - Never exceed the gate-voltage
rating of VGEM. Exceeding the rated VGE can result in
permanent damage to the oxide layer in the gate region.
6. Gate Termination - The gates of these devices are
essentially capacitors. Circuits that leave the gate open-
circuited or floating should be avoided. These conditions
can result in turn-on of the device due to voltage buildup on
the input capacitor due to leakage currents or pickup.
7. Gate Protection - These devices do not have an internal
monolithic Zener diode from gate to emitter. If gate
protection is required an external Zener is recommended.
90%
VGE
VCE
EOFF
10%
EON
90%
ICE
10%
td(OFF)I tfI
trI
td(ON)I
FIGURE 21. SWITCHING TEST WAVEFORMS
Operating Frequency Information
Operating frequency information for a typical device (Figure 3)
is presented as a guide for estimating device performance for
a specific application. Other typical frequency vs collector
current (ICE) plots are possible using the information shown
for a typical unit in Figures 5, 6, 7, 8, 9 and 11. The operating
frequency plot (Figure 3) of a typical device shows fMAX1 or
fMAX2; whichever is smaller at each point. The information is
based on measurements of a typical device and is bounded
by the maximum rated junction temperature.
fMAX1 is defined by fMAX1 = 0.05/(td(OFF)I+ td(ON)I).
Deadtime (the denominator) has been arbitrarily held to 10%
of the on-state time for a 50% duty factor. Other definitions are
possible. td(OFF)I and td(ON)I are defined in Figure 21. Device
turn-off delay can establish an additional frequency limiting
condition for an application other than TJM. td(OFF)I is
important when controlling output ripple under a lightly loaded
condition.
fMAX2 is defined by fMAX2 = (PD - PC)/(EOFF + EON). The
allowable dissipation (PD) is defined by PD = (TJM - TC)/RθJC.
The sum of device switching and conduction losses must not
exceed PD. A 50% duty factor was used (Figure 3) and the
conduction losses (PC) are approximated by
PC = (VCE x ICE)/2.
EON and EOFF are defined in the switching waveforms shown
in Figure 21. EON is the integral of the instantaneous power
loss (ICE x VCE) during turn-on and EOFF is the integral of the
instantaneous power loss (ICE x VCE) during turn-off. All tail
losses are included in the calculation for EOFF; i.e., the
collector current equals zero (ICE = 0).
©2001 Fairchild Semiconductor Corporation
HGTG11N120CND Rev. B
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