ICS342 Просмотр технического описания (PDF) - Integrated Circuit Systems
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ICS342 Datasheet PDF : 7 Pages
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ICS342
Field Programmable Dual Output SS VersaClock
Parameter
Output High Voltage
(CMOS High)
Output High Voltage
Output Low Voltage
Short Circuit Current
Nominal Output
Impedance
Internal pull-up resistor
Internal pull-down
resistor
Input Capacitance
Symbol
Conditions
VOH IOH = -4 mA
VOH
VOL
IOS
ZO
IOH = -12 mA
IOL = 12mA
RPUP
RPD
SEL, PDTS pins
CLK output
CIN Inputs
Min. Typ.
VDD-0.4
Max. Units
V
2.4
V
0.4
V
±70
mA
20
Ω
250
kΩ
525
kΩ
4
pF
Note 1: Example with 25 MHz crystal input with two outputs of 33.3 MHz, no load, and VDD = 3.3 V.
AC Electrical Characteristics
Unless stated otherwise, VDD = 3.3V ±5%, Ambient Temperature -40 to +85° C
Parameter
Symbol
Conditions
Min. Typ. Max. Units
Input Frequency
FIN Fundamental Crystal
5
Input Clock
2
27 MHz
50 MHz
Output Frequency
0.25
200 MHz
Output Rise Time
Output Fall Time
Duty Cycle
tOR 20% to 80%, Note 1
tOF 80% to 20%, Note 1
Note 2
1
ns
1
ns
40 49-51 60
%
Power-up time
PLL lock time from
power-up, Note 3
4
10 ms
PDTS goes high until
stable CLK output, Spread
Spectrum Off, Note 3
0.2
2
ms
PDTS goes high until
stable CLK output, Spread
Spectrum On, Note 3
4
7
ms
One Sigma Clock Period Jitter
Configuration Dependent
50
ps
Maximum Absolute Jitter
tja Deviation from Mean.
+200
ps
Configuration Dependent
Note 1: Measured with 15 pF load.
Note 2: Duty Cycle is configuration dependent. Most configurations are minimum 45% and maximum 55%.
Note 3: ICS test mode output occurs for first 170 clock cycles on CLK2 for each PLL powered up. PDTS
transition high on select address change.
MDS 342 F
5
Revision 090704
Integrated Circuit Systems, Inc. ● 525 Race Street, San Jose, CA 95126 ● tel (408) 297-1201 ● www.icst.com
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