IC41C16100S Просмотр технического описания (PDF) - Integrated Circuit Solution Inc

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IC41C16100S

1M x 16 (16-MBIT) DYNAMIC RAM WITH EDO PAGE MODE

Integrated Circuit Solution Inc 

IC41C16100S

IC41LV16100S

ELECTRICAL CHARACTERISTICS(1)

(Recommended Operating Conditions unless otherwise noted.)

Symbol Parameter

Test Condition

Speed Min.

IIL

Input Leakage Current

Any input 0V ≤ VIN ≤ Vcc

–5

Other inputs not under test = 0V

IIO

Output Leakage Current

Output is disabled (Hi-Z)

–5

0V ≤ VOUT ≤ Vcc

VOH

Output High Voltage Level

IOH = –5.0 mA (5V)

2.4

IOH = –2.0 mA (3.3V)

VOL

Output Low Voltage Level

IOL = 4.2 mA (5V)

—

IOL = 2.0 mA (3.3V)

ICC1

Standby Current: TTL

RAS, LCAS, UCAS ≥ VIH Commerical 5V

—

3.3V —

Extended 5V —

3.3V —

ICC2

Standby Current: CMOS

RAS, LCAS, UCAS ≥ VCC – 0.2V

5V —

3.3V —

ICC3

Operating Current:

RAS, LCAS, UCAS,

Random Read/Write(2,3,4)

Address Cycling, tRC = tRC (min.)

Average Power Supply Current

-45 —

-50 —

-60 —

ICC4

Operating Current:

RAS = VIL, LCAS, UCAS,

EDO Page Mode(2,3,4)

Cycling tPC = tPC (min.)

Average Power Supply Current

-45 —

-50 —

-60 —

ICC5

Refresh Current:

RAS Cycling, LCAS, UCAS ≥ VIH

RAS-Only(2,3)

tRC = tRC (min.)

Average Power Supply Current

-45 —

-50 —

-60 —

ICC6

Refresh Current:

RAS, LCAS, UCAS Cycling

CBR(2,3,5)

tRC = tRC (min.)

Average Power Supply Current

-45 —

-50 —

-60 —

ICCS

Self Refresh Current

Self Refresh mode

—

—

Max.

5

5

—

0.4

2

1

3

2

1

0.5

190

160

145

100

90

80

180

160

145

180

160

145

300

Unit

µA

µA

V

V

mA

mA

mA

mA

mA

mA

mA

µA

Notes:

1. An initial pause of 200 µs is required after power-up followed by eight RAS refresh cycles (RAS-Only or CBR) before proper device

operation is assured. The eight RAS cycles wake-up should be repeated any time the tREF refresh requirement is exceeded.

2. Dependent on cycle rates.

3. Specified values are obtained with minimum cycle time and the output open.

4. Column-address is changed once each EDO page cycle.

5. Enables on-chip refresh and address counters.

Integrated Circuit Solution Inc.

7

DR010-0D 11/26/2004

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