HX6256NSRT Просмотр технического описания (PDF) - Honeywell International
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HX6256NSRT Datasheet PDF : 13 Pages
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HX6256
READ CYCLE AC TIMING CHARACTERISTICS (1)
Symbol
TAVAVR
Parameter
Address Read Cycle Time
Typical
(2)
17
Worst Case (3)
Min
Max
25
Units
ns
TAVQV
Address Access Time
14
25
ns
TAXQX
Address Change to Output Invalid Time
9
3
ns
TSLQV
Chip Select Access Time
17
25
ns
TSLQX
Chip Select Output Enable Time
10
5
ns
TSHQZ
Chip Select Output Disable Time
4
10
ns
TEHQV
Chip Select Access Time (4)
17
25
ns
TEHQX
Chip Select Output Enable Time (4)
10
5
ns
TELQZ
Chip Select Output Disable Time (4)
4
10
ns
TGLQV
Output Enable Access Time
4
9
ns
TGLQX
Output Enable Output Enable Time
4
0
ns
TGHQZ
Output Enable Output Disable Time
2
9
ns
(1) Test conditions: input switching levels VIL/VIH=0.5V/VDD-0.5V (CMOS), VIL/VIH=0V/3V (TTL), input rise and fall times <1 ns/V,
input and output timing reference levels shown in the Tester AC Timing Characteristics table, capacitive output loading CL >50 pF,
or equivalent capacitive output loading CL=5 pF for TSHQZ, TELQZ TGHQZ. For CL >50 pF, derate access times by 0.02 ns/pF
(typical).
(2) Typical operating conditions: VDD=5.0 V, TA=25°C, pre-radiation.
(3) Worst case operating conditions: VDD=4.5 V to 5.5 V, -55 to 125°C, post total dose at 25°C.
(4) Chip Enable (CE) pin not available on 28-lead FP or DIP.
6
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