HX6256NSFT Просмотр технического описания (PDF) - Honeywell International

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HX6256NSFT

32K x 8 Static RAM

Honeywell International 

HX6256

FUNCTIONAL DIAGRAM

SIGNAL DEFINITIONS

A: 0-14 Address input pins which select a particular eight-bit word within the memory array.

DQ: 0-7 Bidirectional data pins which serve as data outputs during a read operation and as data inputs during a write

operation.

NCS

Negative chip select, when at a low level allows normal read or write operation. When at a high level NCS

forces the SRAM to a precharge condition, holds the data output drivers in a high impedance state and disables

all input buffers except CE. If this signal is not used it must be connected to VSS.

NWE

Negative write enable, when at a low level activates a write operation and holds the data output drivers in a high

impedance state. When at a high level NWE allows normal read operation.

NOE

Negative output enable, when at a high level holds the data output drivers in a high impedance state. When at a

low level, the data output driver state is defined by NCS, NWE and CE. If this signal is not used it must be

connected to VSS.

CE*

Chip enable, when at a high level allows normal operation. When at a low level CE forces the SRAM to a

precharge condition, holds the data output drivers in a high impedance state and disables all the input buffers

except the NCS input buffer. If this signal is not used it must be connected to VDD.

TRUTH TABLE

NCS

CE*

L

H

L

H

H

X

X

L

NWE

H

L

XX

XX

NOE

L

X

XX

XX

MODE

Read

Write

Deselected

Disabled

DQ

Data Out

Data In

High Z

High Z

Notes:

X:

VI=VIH or VIL

XX:

VSS≤VI≤VDD

NOE=H: High Z output state

maintained for NCS=X,

CE=X, NWE=X

*Not Available in 28-lead DIP or 28-Lead Flat Pack

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