HT46R52A Просмотр технического описания (PDF) - Holtek Semiconductor
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HT46R52A Datasheet PDF : 43 Pages
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HT46R51A/HT46R52A
Functional Description
Execution Flow
The system clock for the microcontroller is derived from
either a crystal or an RC oscillator. The system clock is
internally divided into four non-overlapping clocks. One
instruction cycle consists of 4 system clock cycles.
Instruction fetching and execution are pipelined in such
a way that a fetch and decoding takes an instruction cy-
cle while execution take the next instruction cycle. The
pipelining scheme causes each instruction to effectively
execute in a cycle. If an instruction changes the program
counter, two cycles are required to complete the instruc-
tion.
Program Counter - PC
For HT46R52A, the program counter (PC) is 11 bits
wide and controls the sequence in which the instructions
stored in the program ROM are executed. The contents
of the PC can specify a maximum of 2048 addresses.
After accessing a program memory word to fetch an in-
struction code, the contents of the program counter are
incremented by one. The program counter then points to
the memory word containing the next instruction code.
When executing a jump instruction, conditional skip ex-
ecution, loading register, subroutine call or return from
subroutine, initial reset, internal interrupt, external inter-
rupt or return from interrupts, the PC manipulates the
program transfer by loading the address corresponding
to each instruction.
For HT46R51A, the program counter (PC) is 10 bits
wide and controls the sequence in which the instructions
stored in the program ROM are executed. The contents
of the PC can specify a maximum of 1024 addresses.
The conditional skip is activated by instructions. Once
the condition is met, the next instruction, fetched during
the current instruction execution, is discarded and a
dummy cycle replaces it to get the proper instruction.
Otherwise proceed to the next instruction.
T1 T2 T3 T4 T1 T2 T3 T4 T1 T2 T3 T4
S y s te m C lo c k
O S C 2 ( R C o n ly )
PC
PC
PC +1
PC +2
F e tc h IN S T (P C )
E x e c u te IN S T (P C -1 )
F e tc h IN S T (P C + 1 )
E x e c u te IN S T (P C )
F e tc h IN S T (P C + 2 )
E x e c u te IN S T (P C + 1 )
Execution Flow
Mode
Initial Reset
External Interrupt
Timer/Event Counter Overflow
A/D Converter Interrupt
Skip
Loading PCL
Jump, Call Branch
Return from Subroutine
Program Counter
*b10 *b9 *b8 *b7 *b6 *b5 *b4 *b3 *b2 *b1 *b0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
1
0
0
0
0
0
0
0
0
0
1
0
0
0
0
0
0
0
0
0
0
1
1
0
0
Program Counter+2
PC10 PC9 PC8 @7 @6 @5 @4 @3 @2 @1 @0
#10 #9 #8 #7 #6 #5 #4 #3 #2 #1 #0
S10 S9 S8 S7 S6 S5 S4 S3 S2 S1 S0
Program Counter
Note:
*b10~*b0: Program counter bits
S10~S0: Stack register bits
#10~#0: Instruction code bits
@7~@0: PCL bits, PC10~PC8: Original PC counter, remain unchanged
For the HT46R51A, since the program counter is 10 bits wide (b0~b9), the b10 columns in the table are not ap-
plicable.
For the HT46R52A, since the program counter is 11 bits wide (b0~b10)
Rev. 1.30
5
March 6, 2009
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