HT1632C(2015) Просмотр технического описания (PDF) - Holtek Semiconductor

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производитель

HT1632C
(Rev.:2015)

32×8 & 24×16 LED Driver

Holtek Semiconductor 

HT1632C

The following are the data mode ID and the command

mode ID:

Operation

Read

Write

Read-Modify-Write

Command

Mode

Data

Data

Data

Command

ID

110

101

101

100

The mode command should be issued before the data

or command is transferred. If successive commands

have been issued, the command mode ID, namely 1

0 0, can be omitted. While the system is operating in

the non-successive command or the non-successive

address data mode, the CS pin should be set to ″1″

and the previous operation mode will be reset also.

Once the CS pin returns to ″0″, a new operation mode

ID should be issued first.

Interfacing

Only four lines are required to interface to the

HT1632C. The CS line is used to initialise the serial

interface circuit and to terminate the communication

between the host controller and the HT1632C. If

the CS pin is set to 1, the data and command issued

between the host controller and the HT1632C are

first disabled and then initialised. Before issuing

a mode command or mode switching, a high level

pulse is required to initialise the serial interface of

the HT1632C. The DATA line is the serial data input/

output line. Data to be read or written or commands

to be written have to be passed through the DATA

line. The RD line is the READ clock input. Data in

the RAM is clocked out on the falling edge of the

RD signal, and the clocked out data will then appear

on the DATA line. It is recommended that the host

controller reads in the correct data during the interval

between the rising edge and the next falling edge

of the RD signal. The WR line is the WRITE clock

input. The data, address, and command on the DATA

line are all clocked into the HT1632C on the rising

edge of the WR signal.

Timing Diagrams

READ Mode − Command Code = 1 1 0

CS

WR

RD

D ATA

1 1 0 A6 A5 A4 A3 A2 A1 A0 D0 D1 D2 D3

M e m o ry A d d re s s 1 (M A 1 ) D a ta (M A 1 )

READ Mode − Successive Address Reading

CS

1 1 0 A6 A5 A4 A3 A2 A1 A0 D0 D1 D2 D3

M e m o ry A d d re s s 2 (M A 2 ) D a ta (M A 2 )

WR

RD

D ATA

1 1 0 A6 A5 A4 A3 A2 A1 A0 D0 D1 D2 D3 D0 D1 D2 D3 D0 D1 D2 D3 D0 D1 D2 D3 D0

M e m o ry A d d re s s (M A ) D a ta (M A ) D a ta (M A + 1 ) D a ta (M A + 2 ) D a ta (M A + 3 )

Rev. 1.60

10

August 19, 2015

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