HT1625 Просмотр технического описания (PDF) - Holtek Semiconductor
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HT1625 Datasheet PDF : 21 Pages
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PATENTED
HT1621/HT1621G
A.C. Characteristics
Ta=25°C
Symbol
Parameter
fSYS1
fSYS2
fSYS3
System Clock
System Clock
System Clock
fLCD
LCD Clock
tCOM
fCLK1
LCD Common Period
Serial Data Clock (WR pin)
Test Conditions
VDD
Conditions
Min.
Typ.
Max. Unit
3V On-chip RC oscillator 192
256
320 kHz
¾ Crystal oscillator
¾
32768
¾
Hz
¾ External clock source ¾
256
¾ kHz
¾ On-chip RC oscillator ¾ fSYS1/1024 ¾
Hz
¾ Crystal oscillator
¾ fSYS2/128 ¾
Hz
¾ External clock source ¾ fSYS3/1024 ¾
Hz
¾ n: Number of COM
¾
n/fLCD
¾
s
3V
Duty cycle 50%
5V
4
¾
150 kHz
4
¾
300 kHz
fCLK2
fTONE
tCS
Serial Data Clock (RD pin)
Tone Frequency (2kHz)
Tone Frequency (4kHz)
Serial Interface Reset Pulse
Width (Figure 3)
3V
Duty cycle 50%
5V
¾
¾
75 kHz
¾
¾
150 kHz
1.5
2.0
2.5 kHz
3V On-chip RC oscillator
3.0
4.0
5.0 kHz
¾ CS
250
300
¾
ns
tCLK
WR, RD Input Pulse Width
(Figure 1)
Write mode
3V
Read mode
Write mode
5V
Read mode
3.34
¾
6.67
¾
1.67
¾
3.34
¾
125
ms
¾
125
ms
¾
tr, tf
Rise/Fall Time Serial Data Clock
Width (Figure 1)
¾
¾
¾
120
160 ns
tSU
Setup Time for DATA to WR, RD
Clock Width (Figure 2)
¾
¾
60
120
¾
ns
th
Hold Time for DATA to WR, RD
Clock Width (Figure 2)
¾
¾
250
300
¾
ns
tsu1
Setup Time for CS to WR, RD
Clock Width (Figure 3)
¾
¾
500
600
¾
ns
th1
Hold Time for CS to WR, RD Clock
Width (Figure 3)
¾
¾
50
100
¾
ns
tOFF
VDD OFF Times (Figure 4)
¾ VDD drop down to 0V 20
¾
¾
ms
tSR
VDD Rising Slew Rate (Figure 4) ¾
¾
0.05
¾
¾ V/ms
tRSTD Delay Time after Reset (Figure 4) ¾
¾
1
¾
¾
ms
Note:
1. If the conditions of Power-on Reset timing are not satisfied in power On/Off sequence, the internal
Power-on Reset (POR) circuit will not operate normally.
2. If the VDD drops below the minimum voltage of operating voltage spec. during operating, the conditions
of Power-on Reset timing must be satisfied also. That is, the VDD must drop to 0V and keep at 0V for
20ms (min.) before rising to the normal operating voltage.
Rev. 2.90
6
November 9, 2010
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