HT1380A Просмотр технического описания (PDF) - Holtek Semiconductor
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HT1380A Datasheet PDF : 14 Pages
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HT1380A/HT1381A
Functional Description
The HT1380A/HT1381A mainly contains the
following internal elements: a data shift register array
to store the clock/calendar data, command control
logic, oscillator circuit and read timer clock. The
clock is contained in eight read/write registers as
shown below. Data contained in the clock register is
in binary coded decimal format.
Two modes are available for transferring the data
between the microprocessor and the HT1380A/
HT1381A. One is in single-byte mode and the other is
in multiple-byte mode.
The HT1380A/HT1381A also contains two additional
bits, the clock halt bit (CH) and the write protect bit (WP).
These bits control the operation of the oscillator and so
data can be written to the register array. These two
bits should first be specified in order to read from and
write to the register array properly.
Command Byte
For each data transfer, a Command Byte is initiated
to specify which register is accessed. This is to
determine whether a read, write, or test cycle is
operated and whether a single byte or burst mode
transfer is to occur. Refer to the table shown below
and follow the steps to write the data to the chip. First
give a Command Byte of HT1380A/HT1381A, and
then write a data in the register.
This table illustrates the correlation between
Command Byte and their bits:
Function Description
Command Byte
C7 C6
C5
C4
C3
C2
Select Read or Write Cycle
——
—
—
—
—
Specify the Register to be Accessed — —
—
—
A2
A1
Clock Halt Flag
C
—
—
—
—
—
For IC Test Only
1
0
0
1
x
x
Select Single Byte or Burst Mode
1
0
1
1
1
1
Note: ″x″ stands for don′t care
The following table shows the register address and its data format:
Register
Name
Range
Data
Register Definition
Address
D7 D6 D5 D4 D3 D2 D1 D0 A2~A0
Seconds
00~59 CH
10 SEC
SEC
000
Minutes
00~59
0
10 MIN
MIN
001
Hours
01~12
00~23
12\ 0
24 0
AP HR
10 HR
HOUR
010
Date
01~31
0 0 10 DATE
DATE
011
Month
01~12
0 0 0 10M
MONTH
100
Day
01~07
000
0
DAY
101
Year
00~99
10 YEAR
YEAR
110
Write Protect 00~80 WP
ALWAYS ZERO
111
C1
C0
—
R/W
A0
—
—
—
x
1
1
x
Bit Command
R/W
Byte
W 10000000
R 10000001
W 10000010
R
10000011
W 10000100
R 10000101
W 10000110
R
10000111
W 10001000
R 10001001
W 10001010
R
10001011
W 10001100
R
10001101
W 10001110
R
10001111
CH: Clock Halt bit
CH=0 oscillator enabled
CH=1 oscillator disabled
WP: Write protect bit
WP=0 register data can be written in
WP=1 register data can not be written in
Bit 7 of Reg2: 12/24 mode flag
bit 7=1, 12-hour mode
bit 7=0, 24-hour mode
Bit 5 of Reg2: AM/PM mode defined
AP=1 PM mode
AP=0 AM mode
Rev. 1.00
5
June 15, 2012
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