HSP45240 Просмотр технического описания (PDF) - Intersil
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HSP45240 Datasheet PDF : 13 Pages
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HSP45240
0
Sequence Generator Functions Normally.
1
Sequence Generator Functions as Shift Register.
CCE - Counter Output Enable: Enable contents of down
counters in the sequence generator control circuitry to be
muxed to the 12 MSBs of the address generator output.
0
Disable Muxing of down counters.
1
Enable Muxing of down counters.
CS - Counter Select: Selects which 12-bit word of the down
counters is muxed to the MSW of the address generator out-
put.
CSl
CS0
0
0
Select Counter 1, bits 0-11.
0
1
Select Counter #1, bits 12-23.
1
0
Select Counter #2, bits 0-11.
1
1
Select Counter #2, bits 12-23.
During reset, this register will be reset to all zeroes. This will
bring the chip up in the mode with all of the test features dis-
abled.
Applications
Image Processing
The application shown in Figure 3 uses the HSP45240
Address Sequencer to satisfy the addressing requirements
for a simple image processing system. In this example the
controller configures the sequencers to generate specialized
addressing sequences for reading and writing the frame
buffers. A typical mode of operation for this system might be
to perform edge detection on a subsection of an image
stored in the frame buffer. In this application, data is fed to
the 2-D Convolver by the address sequence driving the input
frame buffer.
A graphical interpretation of sub-image addressing is shown
in Figure 4. Each dot in the figure corresponds to an image
pixel stored in memory. It is assumed that the pixel values are
stored by row. For example, the first 16 memory locations
would contain the first row of pixel values. The 17th memory
location would contain the first pixel of the second row.
INPUT
FRAME
BUFFER
HSP48808
2D
CONVOLVER
I/O
ADDRESSING
HSP45420 SYNC
SEQUENCER
FRAME OUTPUT
BUFFER
I/O
ADDRESSING
HSP45420
SEQUENCER
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
0
16
32
48
64
80
96
112
128
144
160
178
192
208
224
240
FIGURE 4. SEQUENCER SUB IMAGE ADDRESSING
The sub-image address sequence shown in Figure 3 is gen-
erated by configuring the sequence generator with the fol-
lowing:
1. Start Address
= 35
2. Block Size
=8
3. Number of Blocks = 8
4. Step Size
=1
5. Block Step Size = 16
In this example the start address corresponds to the address
of the first pixel of the first row. The row length corresponds
to the Block Size which is programmed to 8. Within the
block, consecutive addresses are generated by program-
ming the Step Size to 1. At the completion of first block of
addresses, the Block Step Size of 16 is added to the Start
Address to generate the address of the first pixel of the sec-
ond row. Finally, 8 rows of addressing are generated by set-
ting the Number of Blocks to 8.
In this application, the sub-image is processed one time and
then a new sub-image area is chosen. As a result, the Mode
Control Register would be configured for One-Shot mode
without Restart. Also, the Start Delay Control register of the
Sequencer driving the output frame buffer would be config-
ured with a start delay to compensate for the pipeline delay
introduced by the 2-D Convolver. Finally, the crosspoint
switch would be configured in 1:1 mode so that the
sequence generator output has a 1 to 1 mapping to the chip
output.
For applications requiring decimation of the original image,
the Step Size could be increased to provide addressing
which skips over pixels along a row. Similarly, the Block Step
Size could be increased such that pixel rows are skipped.
CONTROLLER
FIGURE 3. IMAGE PROCESSING SYSTEM
FFT Processing
The application shown in Figure 5 depicts the architecture of
a simplified radix 2 FFT processor. In this application the
Address Sequencer drives a memory bank which feeds the
arithmetic processor with data. In a radix 2 implementation,
the arithmetic processor takes two complex data inputs and
8
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