HSP43881 Просмотр технического описания (PDF) - Intersil

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Компоненты Описание

производитель

HSP43881

Digital Filter

Intersil 

HSP43881

Pin Description

SYMBOL

VCC

VSS

CLK

DIN0-7

PIN

NUMBER

A3, A10, B1,

D11, F10, J1,

K4, L7

A1, A11, E2,

F1, E11, H11,

K3, K6, L9

G3

A58, B67, C67

TCS

B5

DIENB

C5

CIN0-7

TCCI

B9-11,

C10-11, D10,

E9-10

A9

CIENB

B8

COUT0-7

TCCO

B2, C1-2,

D1-2, E1, E3,

F2

B3

COENB

A2

TYPE

+5V Power Supply Input.

DESCRIPTION

Power Supply Ground Input.

I

The CLK input provides the DF system sample clock. The maximum clock frequency is 30MHz.

I

These eight inputs are the data sample input bus. Eight bit data samples are synchronously loaded

through these pins to the X register of each filter cell simultaneously. The DIENB signal enables

loading, which is synchronous on the rising edge of the clock signal.

I

The TCS input determines the number system interpretation of the data input samples on pins

DIN0-7 as follows:

TCS = Low → Unsigned Arithmetic.

TCS = High → Two's Complement Arithmetic.

The TCS signal is synchronously loaded into the X register in the same way as the DIN0-7

inputs.

I

A low on this enables the data sample input bus (DIN0-7) to all the filter cells. A rising edge of the

CLK signal occurring while DIENB is low will load the X register of every filter cell with the 8-bit value

present on DIN0-7. A high on this input forces all the bits of the data sample input bus to zero; a

rising CLK edge when DIENB is high will load the X register of every filter cell with all zeros. This

signal is latched inside the DF, delaying its effect by one clock internal to the DF. Therefore, it must

be low during the clock cycle immediately preceding presentation of the desired data on the

DIN0-7 inputs. Detailed operation is shown in later timing diagrams.

I

These eight inputs are used to input the 8-bit coefficients. The coefficients are synchronously load-

ed into the C register of filter CELL 0 if a rising edge of CLK occurs while CIENB is low. The CIENB

signal is delayed by one clock as discussed below.

I

The TCCI input determines the number system interpretation of the coefficient inputs on pins CIN07

as follows:

TCCI = LOW E Unsigned Arithmetic.

TCCI = HIGH E Two's Complement Arithmetic.

The TCCI signal is synchronously loaded into the C register in the same way as the CIN0-7 inputs.

I

A low on this input enable the C register of every filter cell and the D registers (decimation) of every

filter cell according to the state of the DCM0-1 inputs. A rising edge of the CLK signal occurring while

CIENB is low will load the C register and appropriate D registers with the coefficient data present at

their inputs. This provides the mechanism for shifting the coefficients from cell to cell through the

device. A high on this input freezes the contents of the C register and the D registers ignoring the

CLK signal. This signal is latched and delayed by one clock internal to the DF. Therefore, it must be

low during the clock cycle immediately preceding presentation of the desired coefficient of the CIN0-

7 inputs. Detailed operation is shown in the Timing Diagrams Section.

O These eight three-state outputs are used to output the 8-bit coefficients from filter cell 7. These out-

puts are enabled by the COENB signal low. These outputs may be tied to the CIN0-7 inputs of the

same DF to recirculate the coefficients, or they may be tied to the CIN0-7 inputs of another DF to

cascade DFs for longer filter lengths.

O The TCCO three-state output determines the number system representation of the coefficients out-

put on COUTO-7. It tracks the TCCI signal to this same DF. It should be tied to the TCCI input of the

next DF in a cascade of DFs for increased filter lengths. This signal is enabled by COENB low.

I

A low on the COENB input enables the COUT0-7 and the TCCO output. A high on this input places

all these outputs in their high impedance state.

4

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