HSP43124 Просмотр технического описания (PDF) - Intersil

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HSP43124

Serial I/O Filter

Intersil 

HSP43124

in Figure 7. On the following SCLK, the first data bit is

clocked into the Variable Length Shift Register. Data bits are

clocked into the shift register until the data word, of user

programmable length (8 to 24 bits), is complete. At this point,

the shifting of data into the register is disabled and its

contents are held until SYNCIN is asserted on the rising

edge of SCLK. When this occurs, the contents of the

Variable Length Shift Register are transferred to the Input

Holding Register, and the shift register is enabled to accept

serial data on the following SCLK. The serial data word may

be two’s complement or offset binary and may be input most

significant bit (MSB) first or least significant bit (LSB) first as

defined in the Input Format Register (see Table 1). If a data

word is specified to be less than 24 bits, the least significant

bits of the Input Holding Register are zeroed.

NOTE: SYNCIN should not be “high” for longer than

one SCLK cycle.

SCLK

SYNCIN/

SYCNMX

DIN/

MXIN

LSB

SYNC LEADS DATA

LSB

NOTE: Assumes data is being loaded LSB first.

FIGURE 7. SERIAL INPUT TIMING FOR EITHER DIN OR MXIN

INPUTS

Mix Factor

The HSP43124 provides a second serial interface for

loading values which are multiplied by the input samples in

the serial multiplier. These values, or mix factors, are input

using the MXIN and SYNCMX pins. Aside from being used

as a serial input, this interface can also be used to select mix

factors from the Weaver Modulator ROM. The mix factor

source is specified in the Mix Factor Format Register (see

Table 1). NOTE: Data is passed unmodified through the

serial multiplier by selecting the Weaver Modulation ROM

as the mix factor source and tying both SYNCMX and MXIN

“high”.

The procedure for loading serial mix factors is similar to that

for the loading of data via the DIN input. The bit value

present on MXIN is clocked into the Variable Length Shift

register by the rising edge of SCLK. The beginning of the

serial word is designated by the assertion of SYNCMX one

SCLK prior to the first bit of the serial word as shown in

Figure 7. After the serial word has been clocked into the shift

register, the shifting of bits into the register is disabled and

its contents are held until the next assertion of SYNCMX.

When SYNCMX is asserted on the rising edge of SCLK, the

contents of the Variable Length Shift register are transferred

into the Mix Factor Holding Register. The parallel output of

the Mix Factor Holding Register feeds directly into the serial

multiplier. The mix factor data word is programmable in

length from 8 to 24 bits and may be input MSB or LSB first

as specified in the Mix Factor Format Register. If a data

word is specified to be less than 24 bits, the least significant

bits of the Mix Factor Holding Register are zeroed.

The MXIN and SYNCMX inputs can function as two pin

interfaces to Weaver Modulator ROM addresses. Used in

proper sequence, down conversion by FS/4 can be achieved.

These inputs are latched on the rising edge of SCLK when

SYNCIN is high as shown in Figure 9. The mapping of

SYNCIN and MXIN to ROM outputs is given in Table 2.

When SYNCIN is high on the rising edge of SCLK, the

output of the ROM is transferred to the Mix Factor holding

register, and the SYNCMX and MXIN inputs are decoded to

produce a new ROM output. As a result, there is a latency of

one SYNCIN cycle between when the SYNCMX and MXIN

inputs are decoded and when the ROM output is loaded into

the Mix Factor Holding register.

TABLE 2. WEAVER MODULATOR ROM DECODING

SYNCMX

MXIN

MIX FACTOR

0

0

0

0

1

-1

1

0

0

1

1

1

Serial Multiplier

The Serial Multiplier multiplies the Mix Factor Holding

register by the contents of the Input Holding register. The

multiplication cycle is initiated when SYNCIN is sampled

high by the rising edge of SCLK. This transfers the contents

of the Variable Length Shift register to the Input Holding

Register, and loads the output of the Mix Factor Holding

Register into the Serial Multiplier. On subsequent SCLKs,

the contents of the Input Holding Register are shifted into the

Serial Multiplier for processing. When the last data bit is

shifted into the multiplier, the multiplication cycle is complete

and the result is written to the Register File on the next rising

edge of FCLK.

The synchronization between a data sample and the mix

factor it is to be multiplied by is dependent on which mix

factor source is specified. For mix factors which are input

serially, the mix factor is loaded concurrently with the data

sample to be multiplied (see Figure 8).

7

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