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HSP43124

Serial I/O Filter

Intersil 

HSP43124

Pin Description

NAME

TYPE

VCC

-

GND

-

DIN

I

SYNCIN

I

SCLK

I

MXIN

I

SYNCMX

I

FCLK

I

FSYNC

I

WR

I

RD

I

A0-2

I

C0-7

I/O

CLKOUT

O

SYNCOUT

O

DOUT

O

DESCRIPTION

+5V Power Supply

Ground

Serial Data Input. The bit value present on this input is sampled on the rising edge of SCLK. A “HIGH” on this input

represents a “1”, and a low on this input represents “0”. The word format and operation of serial interface are con-

tained in the Data Input Section.

Data Sync. The HSP43124 is synchronized to the beginning of a new data word on DIN when SCLK samples SYN-

CIN “HIGH” one SCLK before the first bit of the new word. NOTE: SYNCIN should not maintain a “HIGH” state

for longer than one SCLK cycle.

Serial Input CLK. The rising edge of SCLK clocks data on DIN and MXIN into the part. The following signals are

synchronous to this clock: DIN, SYNCIN, MXIN, SYNCMX.

Mix Factor Input. MXIN is the serial input for the mix factor. It is sampled on the rising edge of SCLK. A “HIGH” on

this input represents a “1”, and a low on this input represents “0”. Also used to specify the Weaver Modulator ROM

output as a part of the two pin FS/4 down conversion interface. Details on word format and operation are contained

in the Mix Factor Section.

Mix Factor Sync. The HSP43124 is synchronized to the beginning of a serially input mix factor when SCLK samples

SYNCMX “HIGH” one SCLK before the first bit of the new mix factor. NOTE: SYNCMX should only pulse “HIGH”

for one SCLK cycle. Also used to specify Weaver Modulator ROM output as a part of the two pin FS/4 down

conversion interface.

Filter Clock. The filter clock determines the processing speed of the Filter Compute Engine. Clock rate require-

ments on FCLK for particular filter configurations is discussed in the Filter Compute Engine Section. This clock

may be asynchronous to the serial input clock (SCLK). FSYNC is synchronous to this clock.

Filter Sync. This input, when sampled low by the rising edge of FCLK, resets the filter compute engine so that the

data sample following the next SYNCIN cycle is the first data sample into the filter structure. If a data stream is

currently being input, the current sum of products and the input data are “canceled” and the DIN pin is ignored until

the next SYNCIN cycle occurs.

Write. The falling edge of WR loads data present on C0-7 into the configuration or coefficient register specified by

the address on A0-2. The WR signal is asynchronous to all other clocks. NOTE: WR should not be low when

RD is low.

Read. The falling edge of RD accesses the control registers or coefficient RAM addressed by A0-2 and places

the contents of that memory location on C0-7. When RD returns “HIGH” the C0-7 bus functions as an input bus.

The RD pin is asynchronous to all other clocks. NOTE: RD should not be low when WR is low.

Address Bus. The A0-2 inputs are decoded on the falling edge of both RD and WR. Table 1 shows the address

map for the control registers.

Control and Coefficient bus. This bidirectional bus is used to access the control registers and coefficient RAM.

Output Clock. Programmable bit clock for serial output. NOTE: Assertion of FSYNC initializes CLKOUT to a

high state.

Output Data Sync. SYNYOUT is asserted HIGH for one CLKOUT cycle before the first bit of a new output sample

is available on DOUT.

Serial Data Output. The bit stream is synchronous to the rising edge of CLKOUT. (See the Serial Output Formatter

section for additional details.)

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