HS3140 Просмотр технического описания (PDF) - Signal Processing Technologies

Номер в каталоге

Компоненты Описание

производитель

HS3140

14-Bit Multiplying DACs

Signal Processing Technologies 

2 - 1(MSB)

2 -2

0

0

0

1

1

0

1

1

Output

0

1/4 Full-Scale

1/2 Full-Scale

3/4 Full-Scale

Table 1. Contribution of the two MSB's

accuracy required of any switch for a given overall

converter accuracy.

With the decoded converter described above, a 1%

change in any of the converter’s switches will affect

the output by no more than 0.25% of full-scale as

compared to 0.5% for a conventional converter. In

other words the conventional D/A converter can be

made less sensitive to the quality of its individual bits

by decoding.

In the SP7514/HS3140 the first four MSB’s are

decoded into 16 levels which drive 15 equally weighted

current sources. The sensitivity of each switch on the

output is reduced by a factor of 8. Each of the 15

sources contributes 6.25% output change rather than

an MSB change of 50% for the common approach.

Following the decoded section of the DAC a standard

binary weighted R-2R approach is used. This divides

each of the 16 levels (or 6.25% of F.S.) into 4096

discrete levels (the 12 LSB’s).

Output Capacitance

The SP7514/HS3140 have very low output capaci-

tance (CO). This is specified both with all switches ON

and all switches OFF. Output capacitance varies from

50pF to 100pF over all input codes. This low capaci-

tance is due in part to the decoding technique used.

Smaller switches are used with resulting less capaci-

tance. Three important system characteristics are

affected by CO and ∆CO; namely digital feedthrough,

TRANSFER FUNCTION (N=14)

BINARY INPUT UNIPOLAR OUTPUT BIPOLAR OUTPUT

111...111

100...001

100...000

011...111

000…001

000...000

–VREF (1 - 2–N)

–VREF (1/2 + 2–N)

–VREF /2

–VREF (1/2 – 2–N)

–VREF (2(N – 1))

0

–VREF (1 – 2 –(N – 1))

–VREF (2 –(N – 1))

0

VREF (2 ) –(N – 1)

VREF (1 – 2 –(N – 1))

VREF

Table 2. Transfer Function

Corporation

SIGNAL PROCESSING EXCELLENCE

400Ω

V REF

470Ω

V DD

DIGITAL

INPUTS

SP7514

HS3140

RFEEDBACK

I O1

I O2

200Ω

ROS

-

A

+

V OUT

GND

Figure 2. Unipolar Operation

settling time, and bandwidth. The DAC output equiva-

lent circuit can be represented as shown in Figure 1.

Digital feedthrough is the change in analog output due

to the toggling conditions on the converter input data

lines when the analog input VREF is at 0V. The

SP7514/HS3140 very low CO and therefore will yield

low digital feedthrough. Inputs to the DAC can be

buffered. This input latch with microprocessor control

is shown in Figure 4.

Settling time is directly affected by CO. In Figure 1, CO

combines with Rf to add a pole to the open loop

response, reducing bandwidth and causing excessive

phase shift - which could result in ringing and/or

oscillation. A feedback capacitor, Cf must be added to

restore stability. Even with Cf, there is still a zero-pole

mismatch due to RiCO which is code dependent. This

code dependent mismatch is minimized when CORi =

RfCf. However Cf must now be made larger to

compensate for worst case ∆RiCO - resulting in re-

duced bandwidth and increased settling time. With the

SP7514/HS3140, small values for Cf must be used.

400Ω

V REF

470Ω

V DD

200Ω

R FEEDBACK

I O1

DIGITAL

INPUTS

SP7514

HS3140

4KΩ

4KΩ

IO2

GND

ROS2 R

R OS2

-

A2

+

R OS1

-

A1

+

VOUT

V OUT1

A1, A2 , OP-07

Figure 3. Bipolar Operation

163

Share Link: