HS3140B-4/833 Просмотр технического описания (PDF) - Signal Processing Technologies
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HS3140B-4/833 Datasheet PDF : 8 Pages
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D0
D1
D2
D3
D4
D5
D6
D7
WR G2A
74LS138
BDSEL
A2
A1
A0
G2B
C
B
A
ADDRESS DECODER
VREF
(+ 25V MAX) 400
D0
D1
D2
74273 D3
D4
D5
D6
CLK D7
LSB VREF
15 +VDD
14
13 RF
12
11
10 I01
9 I02
D0
D1
D2
74273 D3
D4
D5
D6
CLK D7
SSPP77551144//
H7S5311640
8
7
6
5
4
3
2
MSB GND
VDD
470 3
UNIPOLAR MODE
(2-QUADRANT)
200
2
–
3 +A1
6
VOUT
0 TO - V REF
(1-2 - N)
R0S
LATCHES
Figure 4. Microprocessor Interface to SP7514/HS3140
Resistor Rp can be added, this will parallel Rj decreas-
ing the effective resistance. If Cf is reduced the
bandwidth will be increased and settling time de-
creased. However a system penalty for lowering Cf is
to increase noise gain. The trade-off is noise vs.
settling time. If Rp is added then a large value (1µF or
greater) non-polarized capacitor Cp should be added
in series with Rp to eliminate any DC drifts. If settling
time is not important, eliminate Rp and Cp, and adjust
Cf to prevent overshoot.
Output Offset
In most applications, the output of the DAC is fed into
an amplifier to convert the DAC’s current output to
voltage. A little known and not commonly discussed
parameter is the linearity error versus offset voltage of
the output amplifier. All CMOS DAC’s must operate
into a virtual ground, i.e., the summing junction of an
op amp. Any amplifier’s offset from the amplifier will
appear as an error at the output (which can be related
to LSB’s of error).
Most all CMOS DAC’s currently available are imple-
mented using an R-2R ladder network. The formula
for nonlinearity is typically 0.67mV/mVOS (not de-
rived here). However the SP7516 has a coefficient of
only 0.065mV/mVOS. This is due to the decoding
technique described earlier. CMOS DAC applica-
tions notes (including this one) always show a poten-
tiometer used to null out the amplifier’s offset. If an
amplifier is chosen having ‘pretrimmed’ offset it may
be possible to eliminate this component. Consider the
following calculations:
1. Using LF441A amplifier (low power - 741 pinout)
2. Specified offset: 0.5mV max
3. Temperature coefficient of input offset: 10µV/°C max
VOS max (0°C to 70°C) = 0.5mV + (70µV)10
= 1.2mV
Add'l nonlinearity (max.) = 1.2mV x 0.065mV/mV
=
78µV (1/2 LSB @ 16 Bits)
Where: 78µV = 1/2 LSB @ 16 Bits (10V range)
Via the above configuration, the SP7514/HS3140
can be used to divide an analog signal by digital code
(i.e. for digitally controlled gain). The transfer func-
tion is given in Table 2, where the value of each bit is
0 or 1. Division by all “0”s is undefined and causes the
op amp to saturate.
Applications Information
Unipolar Operation
Figure 2 shows the interconnections for unipolar
operation. Connect IO1 and FB1 as shown in diagram.
Tie IO2 (Pin 7), FB3 (Pin 3), and FB4 (Pin 1) to Ground
(Pin 8). As shown, a series resistor is recommended in
the VDD supply line to limit current during ‘turn-on’.
To maintain specified linearity, external amplifiers
must be zeroed. Apply an ALL “ZEROES” digital
input and adjust ROS for VOUT = 0 ± 1mV. The
SP7514 and HS3140 have been used successfully
with OP-07, OP-27 and LF441A. For high speed
applications the SP2525 is recommended.
Bipolar Operation
Figure 3 shows the interconnections for bipolar op-
eration. Connect IO1, IO2, FB1, FB3, FB4 as shown in
diagram. Tie LDTR to IO2. As shown, a series resistor
is recommended in the VDD supply line to limit current
during ‘turn-on. To maintain specified linearity, exter-
nal amplifiers must be zeroed. This is best done with
VREF set to zero and, the DAC register loaded with
10...0 (MSB = 1). Set R0S1 for V01 = 0. Set R0S2 for
VOUT = 0. Set VREF to +10V and adjust RB for VOUT
to be 0V.
Grounding
Connect all GND pins to system analog ground
and tie this to digital ground. All unused input pins
must be grounded.
164
Corporation
SIGNAL PROCESSING EXCELLENCE
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