TTSI4K32T3BAL Просмотр технического описания (PDF) - Agere -> LSI Corporation

Номер в каталоге

Компоненты Описание

производитель

TTSI4K32T3BAL

4096-Channel, 32-Highway Time-Slot Interchanger

Agere -> LSI Corporation 

Data Sheet

June 2000

TTSI4K32T

4096-Channel, 32-Highway Time-Slot Interchanger

List of Figures

Figures

Page

Figure 1. Block Diagram of the TTSI4K32T .............................................................................................................6

Figure 2. 217-Pin PBGA (Bottom View) ...................................................................................................................7

Figure 3. A Typical TSI Application ........................................................................................................................15

Figure 4. An 8K Time-Slot Switch Made from 4K TSIs ..........................................................................................17

Figure 5. Asynchronous Read................................................................................................................................18

Figure 6. Asynchronous Write................................................................................................................................18

Figure 7. Synchronous Read .................................................................................................................................19

Figure 8. Synchronous Write..................................................................................................................................19

Figure 9. Mixed-Highway Data Rates ....................................................................................................................20

Figure 10. Virtual and Physical Frames .................................................................................................................21

Figure 11. Synchronization to FSYNC ...................................................................................................................22

Figure 12. Highway Offsets ....................................................................................................................................23

Figure 13. Mixed Low-Latency and Frame-Integrity Modes ...................................................................................27

Figure 14. Block Diagram of the TTSI4K32T's Boundary-Scan Test Logic ...........................................................30

Figure 15. BS TAP Controller State Diagram.........................................................................................................31

Figure 16. Asynchronous Read Cycle Timing Using DT Handshake.....................................................................56

Figure 17. Asynchronous Write Cycle Timing Using DT Handshake .....................................................................56

Figure 18. Asynchronous Read Cycle Timing Using Only CS ...............................................................................57

Figure 19. Asynchronous Write Cycle Timing Using Only CS ...............................................................................57

Figure 20. Synchronous Read Cycle Timing..........................................................................................................58

Figure 21. Synchronous Write Cycle Timing ..........................................................................................................58

Figure 22. TDM Highway Timing............................................................................................................................60

Figure 23. JTAG Interface Timing ..........................................................................................................................61

Lucent Technologies Inc.

3

Share Link: