HM5117400B Просмотр технического описания (PDF) - Hitachi -> Renesas Electronics

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HM5117400B

4,194,304-word 4-bit Dynamic Random Access Memory

Hitachi -> Renesas Electronics 

HM5117400B Series

10. Assumes that tRCD tRCD (max) and tRCD + tCAC (max) tRAD + tAA (max).

11. Assumes that tRAD tRAD (max) and tRCD + tCAC (max) tRAD + tAA (max).

12. Either tRCH or tRRH must be satisfied for a read cycles.

13. tOFF (max) and tOEZ (max) define the time at which the outputs achieve the open circuit condition and

are not referred to output voltage levels.

14. t , WCS t , RWD t , CWD tAWD and tCPW are not restrictive operationg parameters. They are included in the data

sheet as electrical characteristics only; if tWCS tWCS (min), the cycle is an early write cycle and the

data out pin will remain open circuit (high impedance) throughout the entire cycle; if tRWD tRWD

(min), tCWD tCWD (min), and tAWD tAWD (min), or tCWD tCWD (min), tAWD tAWD (min) and tCPW tCPW

(min), the cycle is a read-modify-write and the data output will contain data read from the selected

cell; if neither of the above sets of conditions is satisfied, the condition of the data out (at access

time) is indeterminate.

15. These parameters are referred to

leading edge in early write cycles and to

in delayed write or read-modify-write cycles.

leading edge

16. tRASP defines

pulse width in fast page mode cycles.

17. Access time is determined by the longest among tAA, tCAC and t . CPA

18. In delayed write or read-modify-write cycles, must disable output buffer prior to applying data to

the device. After

is reset, if tOEH tCWL, the I/O pin will remain open circuit (high impedance);

if tOEH < tCWL, invalid data will be out at each I/O.

19. The 16M DRAM offers a 16-bit time saving parallel test mode. Address CA0 and CA1 for the 4M

4 are don’t care during test mode. Test mode is set by performing -and- -before-

(WCBR) cycle. In 16-bit parallel test mode, data is written into 4 bits in parallel at each I/O (I/O1 to

I/O4) and read out from each I/O.

If 4 bits of each I/O are equal (all 1s or 0s), data output pin is a high state during test mode read

cycle, then the device has passed. If they are not equal, data output pin is a low state, then the

device has failed.

Refresh during test mode operation can be performed by normal read cycles or by WCBR refresh

cycles.

To get out of test mode and enter a normal operation mode, perform either a regular

refresh cycle or -only refresh cycle.

-before-

20. In a test mode read cycle, the value of tRAC, tAA, tCAC and tCPA is delayed by 2 ns to 5 ns for the

specified value. These parameters should be specified in test mode cycles by adding the above

value to the specified value in this data sheet.

21 XXX: H or L (H: VIH (min) VIN VIH (max), L: VIL (min) VIN VIL (max))

///////: Invalid Dout

11

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