HI5766(1999) Просмотр технического описания (PDF) - Intersil
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HI5766 Datasheet PDF : 14 Pages
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HI5766
Electrical Specifications
ACVLC=C1=0pDFV; CTCA1==255.o0CV;,
DVCC2 = 3.0V; VREF+ =
Differential Analog Input;
2.5V; VREF - =
Typical Values
2.0V; fS
are Test
= 60 MSPS at 50%
Results at 25oC,
Duty
Cycle;
Unless Otherwise Specified (Continued)
PARAMETER
TEST CONDITIONS
Offset Error Sensitivity, ∆VOS
Gain Error Sensitivity, ∆FSE
NOTES:
AVCC or DVCC = 5V ±5%
AVCC or DVCC = 5V ±5%
2. Parameter guaranteed by design or characterization and not production tested.
3. With the clock low and DC input.
MIN
TYP
MAX
UNITS
-
±0.4
-
LSB
-
±0.8
-
LSB
Timing Waveforms
ANALOG
INPUT
CLOCK
INPUT SN - 1 HN - 1 SN
HN SN + 1 HN + 1 SN + 2
SN + 5 HN+5 SN + 6 HN + 6 SN + 7 HN + 7 SN + 8 HN + 8
INPUT
S/H
1ST
STAGE
2ND
STAGE
B1, N - 1
B1, N
B1, N + 1
B2, N - 2
B2, N - 1
B2, N
B1, N + 4
B1, N + 5
B1, N + 6
B1, N + 7
B2, N + 4
B2, N + 5
B2, N + 6
9TH
STAGE
B9, N - 5
B9, N - 4
B9, N
B9, N + 1
B9, N + 2
B9, N + 3
DATA
OUTPUT
DN - 7
DN - 6
DN - 2
DN - 1
DN
tLAT
NOTES:
4. SN: N-th sampling period.
5. HN: N-th holding period.
6. BM, N: M-th stage digital output corresponding to N-th sampled input.
7. DN: Final data output corresponding to N-th sampled input.
FIGURE 1. HI5766 INTERNAL CIRCUIT TIMING
DN + 1
36
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