HI-8282ACLT(2001) Просмотр технического описания (PDF) - Holt Integrated Circuits
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HI-8282ACLT Datasheet PDF : 14 Pages
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HI-8282A
Vcc = 5V, GND = 0V, TA = Operating Temperature Range and fclk = 1MHz +0.1% with 60/40 duty cycle
PARAMETER
CONTROL WORD TIMING
Pulse Width - CWSTR
Setup - DATA BUS Valid to CWSTR HIGH
Hold - CWSTR HIGH to DATA BUS Hi-Z
RECEIVER TIMING
Delay - Start ARINC 32nd Bit to D/R LOW: High Speed
Low Speed
Delay - D/R LOW to EN L0W
Delay - EN LOW to D/R HIGH
Setup - SEL to EN L0W
Hold - SEL to EN HIGH
Delay - EN L0W to DATA BUS Valid
Delay - EN HIGH to DATA BUS Hi-Z
Pulse Width - EN1 or EN2
Spacing - EN HIGH to next EN L0W
FIFO TIMING
Pulse Width - PL1 or PL2
Setup - DATA BUS Valid to PL HIGH
Hold - PL HIGH to DATA BUS Hi-Z
Spacing - PL1 or PL2
Delay - PL2 HIGH to TX/R LOW
TRANSMISSION TIMING
SYMBOL
tCWSTR
tCWSET
tCWHLD
tD/R
tD/R
tD/REN
tEND/R
tSELEN
tENSEL
tENDATA
tDATAEN
tEN
tENEN
tPL
tDWSET
tDWHLD
tPL12
tTX/R
LIMITS
MIN
TYP
130
130
0
0
20
20
200
50
200
110
0
0
Spacing - PL2 HIGH to ENTX HIGH
tPL2EN
0
Delay - ENTX HIGH to 429DO or 429D0: High Speed
Delay - ENTX HIGH to 429DO or 429D0: Low Speed
tENDAT
tENDAT
Delay - 32nd ARINC Bit to TX/R HIGH
tDTX/R
Spacing - TX/R HIGH to ENTX L0W
tENTX/R
0
REPEATER OPERATION TIMING
Delay - EN LOW to PL LOW
tENPL
0
Hold - PL HIGH to EN HIGH
tPLEN
0
Delay - TX/R LOW to ENTX HIGH
tTX/REN
0
Master Reset Pulse Width
tMR
200
ARINC Data Rate and Bit Timing
UNITS
MAX
ns
ns
ns
16
µs
128
µs
ns
200
ns
ns
ns
200
ns
30
ns
ns
ns
ns
ns
ns
ns
840
ns
µs
25
µs
200
µs
400
ns
ns
ns
ns
ns
ns
± 1%
HOLT INTEGRATED CIRCUITS
9
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