HFA3926 Просмотр технического описания (PDF) - Intersil
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HFA3926 Datasheet PDF : 7 Pages
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HFA3926
Pin Description
PINS
SYMBOL
DESCRIPTION
1
GND
DC and RF Ground.
2
GND
DC and RF Ground.
3
GND
DC and RF Ground.
4
GND
DC and RF Ground.
5
GND
DC and RF Ground.
6
GND
DC and RF Ground.
7
GND
DC and RF Ground.
8
No connect.
9
VG2
Negative bias control for the second PA stage, adjusted to set VDD2 quiescent bias current, which is typically
53mA. Typical voltage at pin = -0.75V. Input impedance: > 1MΩ.
10
GND
DC and RF Ground.
11
VDD1
Positive bias for the first stage of the PA, 2.7V to 6V.
12
GND
DC and RF Ground.
13
GND
DC and RF Ground.
14
VG1
Negative bias control for the first PA stage, adjusted to set VDD1 quiescent bias current, which is typically
20mA. Typical voltage at pin = -0.75V. Input impedance: > 1MΩ.
15
RF IN
RF Input of the Power Amplifier.
16S
GND
DC and RF Ground.
17
VG3
Negative bias control for the third PA stage, adjusted to set VDD3 quiescent bias current, which is typically
90mA. Typical voltage at pin = -0.95V. Input impedance: > 1MΩ.
18
19-22
VDD2
GND
Positive bias for the second stage of the PA. 2.7V to 6V.
DC and RF Ground.
23
VDD3
Positive bias for the third stage of the PA. 2.7V to 6V.
24
GND
DC and RF Ground.
25
RF OUT
RF output of power amplifier.
26
GND
DC and RF Ground.
27
VDD
VDD.
28
GND
DC and RF Ground.
NOTE: Process variation will effect VG3 voltage requirement to develop 90mA stage 3 quiescent current, maximum range = -0.69V to -1.04V.
2-230
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