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HEF4527B

BCD rate multiplier

Philips Electronics 

Philips Semiconductors

BCD rate multiplier

Product specification

HEF4527B

MSI

DESCRIPTION

The HEF4527B is a BCD rate multiplier with two buffered

rate outputs (O1 and O1), two buffered terminal count

outputs (TC and TC), four BCD rate select inputs (SA, SB,

SC, SD), a common clock input (CP), a preset input (PL),

an overriding asynchronous clear input (CL), a strobe input

(STR), a cascade input (CAS) and an active LOW count

enable input (CE).

The BCD rate multiplier provides an output pulse rate

based upon the BCD input number. For example, if 6 is the

BCD number, there will be six output pulses for every ten

clock input pulses. The output is clocked on the

negative-going transition of the clock.

When CE, STR, CAS, CL and PL are LOW, the rate pulses

are available at the outputs O1 and O1, the terminal count

pulses at TC and TC.

A HIGH on CL resets the counter, independent of all other

input conditions and a rate of 10 pulses is available at O1

and O1 when SD is HIGH. When CE is HIGH, the counter

is disabled, the state of the outputs (O1, O1) depend on the

content of the counter.

A HIGH on PL sets the counter in the ‘9’ state and TC

becomes HIGH.

A HIGH on STR inhibits the outputs O1 and O1. A HIGH on

CAS forces the output O1 to HIGH, while the state of

O1 depends on the inputs SA to SD (see lines 1 to 16 of

function table).

This device may be used to perform arithmetic operations.

For the add mode and multiply mode see Figs 5 and 6.

Schmitt-trigger action in the clock input makes the circuit

highly tolerant to slower clock rise and fall times.

Fig.1 Functional diagram.

FAMILY DATA, IDD LIMITS category MSI

See Family Specifications

January 1995

2

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