HEF4027BP Просмотр технического описания (PDF) - NXP Semiconductors.
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HEF4027BP Datasheet PDF : 14 Pages
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NXP Semiconductors
HEF4027B
Dual JK flip-flop
VI
SD INPUT
0V
VI
CD INPUT
0V
VI
CP INPUT
0V
VOH
Q OUTPUT
VOL
VM
tW
trec
VM
VM
tW
Fig 6.
VOH and VOL are typical output voltages levels that occur with the output load.
Measurement points are given in Table 9.
Waveforms showing pulse widths and recovery times
trec
001aae597
Table 9. Measurement points
Supply voltage
VDD
5 V to 15 V
Input
VM
0.5VDD
Output
VM
0.5VDD
VDD
VI
G
VO
DUT
RT
CL
001aag182
Fig 7.
Test data is given in Table 10.
Definitions for test circuit:
DUT = Device Under Test.
CL = load capacitance including jig and probe capacitance.
RT = termination resistance should be equal to the output impedance Zo of the pulse generator.
Test circuit
Table 10. Test data
Supply voltage
VDD
5 V to 15 V
Input
VI
VSS or VDD
tr, tf
20 ns
Load
CL
50 pF
HEF4027B
Product data sheet
All information provided in this document is subject to legal disclaimers.
Rev. 9 — 18 November 2011
© NXP B.V. 2011. All rights reserved.
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