H8/3068F Просмотр технического описания (PDF) - Renesas Electronics
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H8/3068F Datasheet PDF : 935 Pages
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Preface
The H8/3068F is a group of high-performance single-chip microcontrollers that integrate system
supporting functions together with an H8/300H CPU core.
The H8/300H CPU has a 32-bit internal architecture with sixteen 16-bit general registers, and a
concise, optimized instruction set designed for speed. It can address a 16-Mbyte linear address
space.
The on-chip supporting functions include ROM, RAM, 16-bit timers, 8-bit timers, a
programmable timing pattern controller (TPC), a watchdog timer (WDT), a serial communication
interface (SCI), an A/D converter, a D/A converter, I/O ports, a DMA controller (DMAC), and
other facilities. The three-channel SCI has been expanded to support the ISO/IEC7816-3 smart
card interface. Functions have also been added to reduce power consumption in battery-powered
applications: individual modules can be placed in standby, and the frequency of the system clock
supplied to the chip can be divided down under software control.
The address space is divided into eight areas. The data bus width and access cycle length can be
selected independently in each area, simplifying the connection of different types of memory.
Seven MCU operating modes (modes 1 to 7) are provided, offering a choice of data bus width and
address space size.
With these features, the H8/3068F offers easy implementation of compact, high-performance
systems.
The H8/3068F has an F-ZTAT™* version with on-chip flash memory that can be programmed
on-board. This version enables users to respond quickly and flexibly to changing application
specifications.
This manual describes the H8/3068F hardware. For details of the instruction set, refer to the
H8/300H Series Programming Manual.
Note: * F-ZTAT™ (Flexible ZTAT) is a registered trademark of Renesas Technology Corp.
Rev. 3.00 Sep 14, 2005 page iii of xxii
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