HD6413007F(2007) Просмотр технического описания (PDF) - Renesas Electronics
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HD6413007F Datasheet PDF : 796 Pages
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Item
Page
8.8.2 Register
281
Configuration
Port B Data Register
(PBDR):
Table 8.16 Port B Pin
Functions
PB3/TP11/TMIO3/DREQ1/
CS
4
PB2/TP10/TMO2/CS5
282
PB /TP /TMIO /DREQ /
1
9
1
0
CS
6
PB /TP /TMO /CS
283
0
8
0
7
9.1.4 Register
291
Configuration
Table 9.3 16-bit timer
Registers
Revision (See Manual for Details)
Description amended
The DRAM interface settings by bits DRAS2 to DRAS0 in
DRCRA, bits OIS3/2 and OS1/0 in 8TCSR3, bits CCLR1 and
CCLR0 in 8TCR3, bit CS4E in CSCR, bit NDER11 in NDERB,
and bit PB3DDR select the pin function as follows.
Table amended
Pin
PB2/TP10/
TMO2/CS5
Pin Functions and Selection Method
The DRAM interface settings by bits DRAS2 to DRAS0 in DRCRA, bits OIS3/2 and
OS1/0 in 8TCSR2, bit CS5E in CSCR, bit NDER10 in NDERB, and bit PB2DDR
select the pin function as follows.
DRAM interface
settings
OIS3/2 and
OS1/0
(1) in table below
All 0
Not all 0
(2) in
table
below
⎯
CS5E
0
1
⎯
⎯
PB2DDR
NDER10
Pin function
0
⎯
PB2
input
1
0
PB2
output
1
1
TP10
output
⎯
⎯
CS
5
output
⎯
⎯
TMO2
output
⎯
⎯
CS
5
output*
Description amended
Bits OIS3/2 and OS1/0 in 8TCSR1, bits CCLR1 and CCLR0 in
8TCR0, bit CS6E in CSCR, bit NDER9 in NDERB, and bit
PB1DDR select the pin function as follows.
Description amended
Bits OIS3/2 and OS1/0 in 8TCSR0, bit CS7E in CSCR, bit
NDER8 in NDERB, and bit PB0DDR select the pin function as
follows.
Table amended
Channel
Common
Address*1
H'FFF64
Name
Timer interrupt status register A
Abbre-
viation
TISRA
Initial
R/W Value
R/(W)*2 H'88
Rev.5.00 Sep. 12, 2007 Page ix of xxviii
REJ09B0396-0500
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