HD6413007F(2007) Просмотр технического описания (PDF) - Renesas Electronics

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HD6413007F
(Rev.:2007)

16-Bit Single-Chip Microcomputer

Renesas Electronics 

Item

Page

9.4.6 Setting Initial 333

Value of 16-Bit Timer

Output

Figure 9.32 Example of

Timing for Setting Initial

Value of 16-Bit Timer

Output by Writing to

TOLR

Revision (See Manual for Details)

Figure amended

T1

T2

T3

φ

Address bus

TOLR address

TOLR

N

10.2.3 Time Constant 357

Registers B (TCORB)

10.2.4 Timer Control 359

Register (8TCR)

Bits 4 and 3⎯Counter

Clear 1 and 0 (CCLR1,

CCLR0):

Bits 2 to 0⎯Clock

Select 2 to 0 (CSK2 to

CSK0):

10.2.5 Timer

362

Control/Status Registers

(8TCSR)

Bit 7⎯Compare

Match/Input Capture

Flag B (CMFB):

Bit 6⎯Compare Match

Flag A (CMFA):

Bit 4⎯Reserved (In 363

8TCSR1):

Bit 4⎯Input Capture

Enable (ICE) (In

8TCSR1 and 8TCSR3):

16-bit timer output pin

N

Note added

Note: * When channel 1 and channel 3 are designated for

TCORB input capture, the CMFB flag is not set by a

channel 0 or channel 2 compare match B.

Note added

Note: When input capture B is set as the 8TCNT1 and

8TCNT3 counter clear source, 8TCNT0 and 8TCNT2

are not cleared by compare match B.

Description replaced

Note added

Note: * When bit ICE is set to 1 in 8TCSR1 and 8TCSR3, the

CMFB flag is not set when 8TCNT0 = TCORB0 or

8TCNT2 = TCORB2.

Description amended

Status flag that indicates the occurrence of a TCORA compare

match .

Description replaced

Rev.5.00 Sep. 12, 2007 Page x of xxviii

REJ09B0396-0500

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