6N135SM Просмотр технического описания (PDF) - Fairchild Semiconductor
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6N135SM Datasheet PDF : 13 Pages
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PRELIMINARY
Test Circuits
Pulse
Generator
tr = 5ns
IF
ZO = 50 Ω
10% D.C.
I/f < 100µs
Noise
Shield
1
+
2
VF
-
3
IF Monitor
Rm
4
8 VCC
7 VB
+5 V
RL
Pulse
Generator
IF +
tr = 5ns
1
ZO = 50 Ω
10% DUTY CYCLE
I/f < 100µS
VF1
-2
6 VO
0.1 µF
5
GND
VO
CL = 1.5 µF
IF
MONITOR
Rm
-3
VF2
+
4
Noise
Shield
VCC
8
RL
V01
7
V02
6
+5 V
VO
CL = 1.5 µF
GND
5
0.1 µF
Test Circuit for 6N135M, 6N136M, HCPL2503M, HCPL4502M and HCPL4503M
IF
0
Test Circuit for HCPL2530M and HCPL2531M
VO
5V
TPHL
1.5 V
1.5 V
VOL
TPLH
Fig. 7 Switching Time Test Circuit
IF
A
B
VFF
Noise
Shield
1
+
2
VF
-
3
4
8 VCC
+5 V
7 VB
RL
6 VO
GND
5
VO
0.1 µF
-
+
V-CM
Pulse Gen
Test Circuit for 6N135M, 6N136M, HCPL2503M, HCPL4502M and HCPL4503M
IF
A
B
VFF
+1
VF1
-2
Noise
Shield
-3
VF2
+
4
VCC
8
RL
V01
7
+5 V
VO
V02
6
0.1 µF
GND
5
VCM
+
-
Pulse Gen
Test Circuit for HCPL2530M and HCPL2531M
VCM 10 V
10 %
0V
tr
90% 90%
10 %
tf
VO
5V
Switch at A : IF = 0 mA
VO
VOL
Switch at A : IF = 16 mA
Fig. 8 Common Mode Immunity Test Circuit
©2008 Fairchild Semiconductor Corporation
6N13XM, HCPLXXXM Rev. 1.0.1
8
www.fairchildsemi.com
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