HCF40103BC1 Просмотр технического описания (PDF) - STMicroelectronics

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HCF40103BC1

8-STAGE PRESETTABLE SYNCHRONOUS DOWN COUNTERS

STMicroelectronics 

HCC/HCF40102B/40103B

LOGIC DIAGRAMS (continued)

Timing Diagram for 40102B and 40103B

40102B

TRUTH TABLE

CLR

Control Inputs

APE SPE CI/CE

Preset Mode

Action

1

1

1

1

1

1

1

0

Synchronous

Inhibit Counter

Count Down

1

1

0

X

Preset on Next Positive Clock Transition

1

0

X

X

0

X

X

X

Asynchronous

Preset Asynchrounously

Clear to Maximum Count

Notes :

1. 0 = Low level

1 = High level

X = Don’t care

2. Clock connected to clock input.

3. Synchronous operation : changes occur on negative-to-positive clock transitions..

JAM inputs : HCC/HCF010B ; MSD = J7, J6, J5, J4 (J7 is MSB)

LSD = J3, J2, J1, J0 (J3 is MSB)

HCC/HCF40103B Binary ; MSB = J7, LSB = J0

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