HC-5560 Просмотр технического описания (PDF) - Intersil

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производитель

HC-5560

PCM Transcoder

Intersil 

Timing Waveforms (Continued)

HC-5560

tFCL

CLK DEC

10%

1

fCL

90%

tRCL

50%

tS

tH

AIN, BIN

50%

CLOCK

NRZ DATA OUT

50%

tDD

50%

FIGURE 2. RECEIVER (DECODER) TIMING WAVEFORMS

CLK DEC

RESET AIS

50%

tH2

50%

tS2 tPD5

tS2

50%

50%

AIS OUTPUT

tPD4

50%

ERROR OUTPUT

50%

FIGURE 3. RESET AIS INPUT, AIS OUTPUT, ERROR OUTPUT

CLK DEC

RESET AIS

NRZ DATA OUT

AIS

FIGURE 4.

Two consecutive periods of Reset AIS, each containing less than three zeros, sets AIS to a logic ‘1’ and remains in a logic ‘1’ state

until a period of Reset AIS contains three or more zeros.

7

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