HD64F2602 Просмотр технического описания (PDF) - Renesas Electronics
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HD64F2602 Datasheet PDF : 492 Pages
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2.7.8 Memory Indirect—@@aa:8 ................................................................................... 40
2.7.9 Effective Address Calculation ................................................................................ 41
2.8 Processing States.................................................................................................................. 43
2.9 Usage Notes ......................................................................................................................... 44
2.9.1 Usage Notes on Bit Manipulation Instructions ....................................................... 44
Section 3 MCU Operating Modes ....................................................................... 45
3.1 Operating Mode Selection ................................................................................................... 45
3.2 Register Descriptions........................................................................................................... 45
3.2.1 Mode Control Register(MDCR) ............................................................................. 46
3.2.2 System Control Register(SYSCR).......................................................................... 47
3.3 Pin Functions in Each Operating Mode ............................................................................... 48
3.3.1 Pin Functions .......................................................................................................... 48
3.4 Address Map ........................................................................................................................ 49
Section 4 Exception Handling ............................................................................. 51
4.1 Exception Handling Types and Priority............................................................................... 51
4.2 Exception Sources and Exception Vector Table .................................................................. 51
4.3 Reset .................................................................................................................................... 53
4.3.1 Reset Exception Handling ...................................................................................... 53
4.3.2 Interrupts after Reset............................................................................................... 56
4.3.3 State of On-Chip Supporting Modules after Reset Release .................................... 56
4.4 Traces................................................................................................................................... 57
4.5 Interrupts.............................................................................................................................. 57
4.6 Trap Instruction.................................................................................................................... 58
4.7 Stack Status after Exception Handling................................................................................. 59
4.8 Usage Note........................................................................................................................... 60
Section 5 Interrupt Controller.............................................................................. 61
5.1 Features................................................................................................................................ 61
5.2 Input/Output Pins................................................................................................................. 63
5.3 Register Descriptions........................................................................................................... 63
5.3.1 Interrupt Priority Registers A to H, J, K, M
(IPRA to IPRH, IPRJ, IPRK, IPRM)...................................................................... 64
5.3.2 IRQ Enable Register (IER) ..................................................................................... 65
5.3.3 IRQ Sense Control Registers H and L (ISCRH, ISCRL)........................................ 66
5.3.4 IRQ Status Register (ISR)....................................................................................... 68
5.4 Interrupt ............................................................................................................................... 69
5.4.1 External Interrupts .................................................................................................. 69
5.4.2 Internal Interrupts ................................................................................................... 70
Rev. 1.00 Jan. 21, 2008 Page x of xxxii
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