GS9092A Просмотр технического описания (PDF) - Gennum -> Semtech
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GS9092A Datasheet PDF : 59 Pages
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1.2 Pin Descriptions
GS9092A Data Sheet
Table 1-1: Pin Descriptions
Pin
Number
Name
1
LF-
2
PLL_GND
3
PLL_VDD
4
CD_VDD
5, 6
SDO, SDO
7
CD_GND
8
NC
9
RSET
10
VBG
11
SDO_EN
Timing
Type Description
Analog
Analog
Analog
Analog
Analog
Input
Input
Power
Input
Power
Input
Power
Output
Analog
–
Analog
Input
Power
–
Input
Analog
Input
Non
Input
Synchronous
Loop filter component connection. Connect to LF+ through a capacitor.
See Typical Application Circuit on page 56.
Ground connection for phase-locked loop. Connect to GND.
Power supply connection for phase-locked loop. Connect to +1.8V DC.
Power supply connection for serial digital cable driver. Connect to
+1.8V DC
Serial digital differential output pair.
NOTE: these output signals will be forced into a mute state if RESET is
LOW.
Ground connection for serial digital cable driver. Connect to GND.
No connect.
An external 1% resistor connected between this input and CD_VDD is
used to set the SDO / SDO output amplitude.
Bandgap filter capacitor. Connect as shown in the Typical Application
Circuit on page 56
CONTROL SIGNAL INPUT
Signal levels are LVCMOS / LVTTL compatible
Used to enable or disable the serial digital output.
When set LOW by the application layer, the serial digital output signals
SDO and SDO are muted.
When set HIGH by the application layer, the serial digital output signals
are enabled.
SDO and SDO outputs will also be high impedance when the RESET
pin is LOW.
34715 - 0 February 2006
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