GS9092 Просмотр технического описания (PDF) - Gennum -> Semtech
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GS9092 Datasheet PDF : 58 Pages
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GS9092 Data Sheet
Table 1-1: Pin Descriptions (Continued)
Pin
Number
Name
Timing
Type Description
23, 25, 26 STAT[0:2]
24, 28, 42 IO_GND
30
WR_CLK
31
WR_RESET
32 - 41
DIN[0:9]
44
PCLK
46
RSV
Synchronous
with PCLK or
WR_CLK
Non
Synchronous
Synchronous
with
WR_CLK
Synchronous
with
WR_CLK
or PCLK
–
Input/O
utput
Input
Power
Input
Input
Input
Input
–
MULTI FUNCTION I/O PORT
Signal levels are LVCMOS / LVTTL compatible.
Programmable multi-function I/O. By programming the bits in the
IO_CONFIG register, each pin can act as an output for one of the
following signals:
•H
•V
•F
• FIFO_FULL
• FIFO_EMPTY
Each pin may also act as an input for an external H, V, or F signal if the
DETECT_TRS pin is set LOW by the application layer
These pins are set to certain default values depending on the
configuration of the device and the internal FIFO mode selected. See
Programmable Multi-function I/O on page 46 for details.
Ground connection for digital I/O. Connect to GND.
FIFO WRITE CLOCK
Signal levels are LVCMOS / LVTTL compatible.
The application layer clocks the parallel data into the device on the
rising edge of WR_CLK when the internal FIFO is configured for video
mode or DVB-ASI mode.
NOTE: If this pin is unused it should be pulled up to GND.
FIFO WRITE RESET
Signal levels are LVCMOS / LVTTL compatible.
Valid input only when the device is in SMPTE mode (SMPTE_BYPASS
= HIGH, DVB-ASI = LOW) and the internal FIFO is configured for video
mode (Video Mode on page 23).
A HIGH to LOW transition will reset the FIFO write pointer to address
zero of the memory.
NOTE: If this pin is unused it should be pulled up to GND.
PARALLEL VIDEO DATA BUS
Signal levels are LVCMOS / LVTTL compatible.
When the internal FIFO is enabled and configured for either video
mode or DVB-ASI mode, parallel data will be clocked into the device on
the rising edge of WR_CLK.
When the internal FIFO is in bypass mode, parallel data will be clocked
into the device on the rising edge of PCLK.
DIN9 is the MSB and DIN0 is the LSB.
PIXEL CLOCK INPUT
Signal levels are LVCMOS / LVTTL compatible.
27MHz parallel clock input.
Reserved. Do Not Connect.
28202 - 2 September 2005
9 of 58
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