GS9091B Просмотр технического описания (PDF) - Gennum -> Semtech
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GS9091B Datasheet PDF : 71 Pages
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Table 1-1: Ball List and Description
Ball
Name
A1
LF+
A2, B5, C3,
C4, C5, C6,
C7, C9, D3,
D8, D9, E3,
E8, F8, G8,
G9, H4, H5,
H6, H7, K2
A3
NC
LB_CONT
A4
VCO_VDD
A5
VBG
A6
FIFO_EN
A7
AUTO/MAN
A8
LOCKED
A9
PCLK
Timing
Analog
–
Type
Input
–
Description
Loop filter component connection. Connect to LF- through a 4.4nF
capacitor.
No connect. Not connected internally.
Analog
Input
CONTROL SIGNAL INPUT
Control voltage to fine-tune the loop bandwidth of the PLL.
Analog
Input
Power
Power supply connection for Voltage-Controlled-Oscillator.
Connect to +1.8V DC.
Analog
Input
Bandgap filter capacitor. Connect to GND as shown in Typical
Application Circuit.
Non
Input
Synchronous
CONTOL SIGNAL INPUT
Signal levels are LVCMOS / LVTTL compatible.
Used to enable / disable the internal FIFO.
When FIFO_EN is HIGH, the internal FIFO will be enabled. Data will
be clocked out of the device on the rising edge of the RD_CLK
input pin if the FIFO is in video mode or DVB-ASI mode.
When FIFO_EN is LOW, the internal FIFO is bypassed and parallel
data is clocked out on the rising edge of the PCLK output.
Non
Input
Synchronous
CONTROL SIGNAL INPUT
Signal levels are LVCMOS / LVTTL compatible.
When set HIGH, the GS9091B will operate in Auto mode. The
SMPTE_BYPASS pin becomes an output status signal set by the
device. In this mode, the GS9091B will automatically detect,
reclock, deserialize, and process SMPTE compliant input data.
When set LOW, the GS9091B will operate in Manual mode. The
DVB_ASI and SMPTE_BYPASS pins become input control signals. In
this mode, the application layer must set these two external pins
for the correct reception of either SMPTE or DVB-ASI data. Manual
mode also supports the reclocking and deserializing of data not
conforming to SMPTE or DVB-ASI streams.
Synchronous
with PCLK
Output
STATUS SIGNAL OUTPUT
Signal levels are LVCMOS / LVTTL compatible.
The LOCKED pin will be HIGH whenever the device has correctly
received and locked to SMPTE compliant data in SMPTE mode or
DVB-ASI compliant data in DVB-ASI mode, or when the reclocker
has achieved lock in Data-Through mode.
It will be LOW otherwise. When the pin is LOW, all digital output
signals will be forced to logic LOW levels.
–
Output PIXEL CLOCK OUTPUT
Signal levels are LVCMOS / LVTTL compatible.
27MHz parallel clock output.
GS9091B GenLINX® II 270Mb/s Deserializer for SDI
and DVB-ASI
Data Sheet
38910 - 2
July 2008
6 of 71
Proprietary & Confidential
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