GS9005ACPJ Просмотр технического описания (PDF) - Gennum -> Semtech

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GS9005ACPJ

Serial Digital Receiver

Gennum -> Semtech 

GS9005A Re - clocking Receiver - Detailed Device Description

The GS9005A Reclocking Receiver is a bipolar integrated

circuit containing a built-in cable equalizer and circuitry

necessary to re-clock and regenerate the NRZI serial data

stream.

Packaged in a 28 pin PLCC, the receiver operates from a

single five volt supply at data rates in excess of 400 Mb/s.

Typical power consumption is 500 mW. Typical output jitter is

± 100 ps at 270 Mb/s.

Serial Digital signals are applied to either a built-in analog

cable equalizer via the SDI and SDI inputs (pins 8,9) or via the

direct digital inputs DDI and DDI (pins 5,6).

Cable Equalizer

The Serial Digital signal is connected to the input either

differentially or single ended with the unused input being

decoupled. The equalized signal is generated by passing the

cable signal through a voltage variable filter having a

characteristic which closely matches the inverse cable loss

characteristic. Additionally, the variation of the filter

characteristic with control voltage is designed to imitate the

variation of the inverse cable loss characteristic as the cable

length is varied.

The amplitude of the equalized signal is monitored by a peak

detector circuit which produces an output current with a

polarity corresponding to the difference between the desired

peak signal level and the actual peak signal level. This output

is integrated by an external AGC filter capacitor (AGC

CAP pin 2), providing a steady control voltage for the voltage

variable filter.

A separate signal strength indicator output, (SSI pin 28),

proportional to the amount of AGC is also provided. As the

filter characteristic is varied automatically by the application of

negative feedback, the amplitude of the equalized signal is

kept at a constant level which is representative of the original

amplitude at the transmitter.

The equalized signal is then DC restored, effectively restoring

the logic threshold of the equalized signal to its correct level

irrespective of shifts due to AC coupling.

As the final stage of signal conditioning, a comparator converts

the analog output of the DC restorer to a regenerated digital

output signal.

An OUTPUT 'EYE' MONITOR (pin 16), allows verification of

signal integrity after equalization but before reslicing.

Analog/Digital Select

A 2:1 multiplexer selects either the equalized (analog) signal

or a differential ECL data (digital) signal as input to the

reclocker PLL.

A logical HIGH applied to the Analog/Digital Select input (1)

routes the equalized signal while a logic LOW routes the

direct digital signal to the reclocker.

Phase Locked Loop

The phase comparator itself compares the position of

transitions in the incoming signal with the phase of the local

oscillator (VCO). The error-correcting output signals are fed

to the charge pump in the form of short pulses. The charge

pump converts these pulses into a “charge packet” which is

accurately proportional to the system phase error.

The charge packet is then integrated by the second-order

loop filter to produce a control voltage for the VCO.

During periods when there are no transitions in the signal, the

loop filter voltage is required to hold precisely at its last value

so that the VCO does not drift significantly between corrections.

Commutating diodes in the charge pump keep the output

leakage current extremely low, minimizing VCO frequency

drift.

The VCO is implemented using a current-controlled

multivibrator, designed to deliver good stability, low phase

noise and wide operating frequency capability. The frequency

range is design-limited to ± 10% about the oscillator centre

frequency.

VCO Centre Frequency Selection

The centre frequency of theVCO is set by one of four external

current reference resistors (RVCO0-RVCO3) connected to

pins 13,14,15 or 17. These are selected by two logic inputs

SS0 and SS1 (pins 20, 21) through a 2:4 decoder according

to the following truth table.

SS1

SS0

0

0

Resistor Selected

RVCO0 (13)

0

1

1

0

RVCO1 (14)

RVCO2 (15)

1

1

RVCO3 (17)

As an alternative, the GS9010A Automatic Tuning Sub-system

and the GS9000B or GS9000S Decoder may be used in

conjunction with the GS9005A to obtain adjustment free and

automatic standard select operation (see Figure 20).

With the VCO operating at twice the clock frequency, a clock

phase which is centred on the eye of the locked signal is used

to latch the incoming data, thus maximising immunity to

jitter-induced errors. The alternate phase is used to latch the

output re-clocked data SDO and SDO (pins 25, 24). The true

and inverse clock signals themselves are available from the

SCO and SCO pins 23 and 22.

3

520 - 28 - 11

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