GS8160Z18CGT-250 Просмотр технического описания (PDF) - Giga Semiconductor

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GS8160Z18CGT-250

18Mb Pipelined and Flow Through Synchronous NBT SRAM

Giga Semiconductor 

Preliminary

GS8160Z18/36CT-333/300/250

Pipeline Mode Data I/O State Diagram

Intermediate

BW

R

High Z

(Data In)

D

Intermediate

Intermediate

W

Intermediate

RB

Data Out

(Q Valid)

D

Intermediate

WR

High Z

B

D

Intermediate

Key

Input Command Code

ƒ Transition

Transition

Current State (n) Intermediate State (N+1) Next State (n+2)

Notes:

1. The Hold command (CKE Low) is not

shown because it prevents any state change.

2. W, R, B, and D represent input command

codes as indicated in the Truth Tables.

n

Clock (CK)

n+1

n+2

n+3

Command

ƒ

ƒ

ƒ

ƒ

Current State

Intermediate

State

Next State

Current State and Next State Definition for Pipeline Mode Data I/O State Diagram

Rev: 1.00 9/2004

9/23

Specifications cited are subject to change without notice. For latest documentation see http://www.gsitechnology.com.

© 2004, GSI Technology

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